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Driving INOUT signals

Hi everyone

I'm trying to simulate a design using a testbench tool called HDL bencher which is integrated with Xilinx ISE.

The problem i have is that when i set the value of the INOUT signal in my design, the testbench does not appear to assert it as desired and the port stays at value zero.

Has anyone else had any similar problems with HDL bencher and ISE?

Or does anyone have any recommendations / tips for working with INOUT signals in designs?

Thanks in advance

Mike Nicklas

Reply to
Mike Nicklas
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Can it be that you are initializing this signal in the test bench as zero? Assuming the signal is std_logic try setting it to 'L' or 'Z' instead.

/Mikhail

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Reply to
MM

Hi

tried that too.

No joy unfortunately.

Any other ideas?

Regards

Mike

MM wrote:

Reply to
Mike Nicklas

Post the relevant pieces of your code... Are you saying it works in another simulator?

/Mikhail

--
To reply directly:
matusov at square peg ca
(join the domain name in one word and add a dot before "ca")
Reply to
MM

Hi

here is a copy of the top module entity declaration. The testbench i tried was generated by a tool called HDL Bencher but i also tried using the command line interface on ModelSIM XE to no avail.

entity nueping2 is port ( -- Interface clock. DSP_CLK: in STD_LOGIC; -- Global reset. RSTl: in STD_LOGIC; -- Indicates whether Spartan can receive data. BUSY: in STD_LOGIC; -- Indicates whether Spartan has data to send. EMPTY: in STD_LOGIC; -- Indicates that ADIO is address or data. AS_DSl: in STD_LOGIC; -- Read/Write enable. RENl_WENl: out STD_LOGIC; -- Indicates if Spartan is being read or written to. RDl_WR: out STD_LOGIC; -- Interrupt to Spartan. INTl: out STD_LOGIC; -- Test LEDs. LEDS: out STD_LOGIC_VECTOR (7 downto 0); -- Data IO between Spartan and Virtex. ADIO: inout STD_LOGIC_VECTOR (31 downto 0) ); end nueping2;

I can add in the code from the auto-generated testbench as well if you like?

Mike

MM wrote:

Reply to
Mike Nicklas

This doesn't help much. We need to see how you drive the signal.

like?

Yes, but only the lines relevant to the signal of interest...

/Mikhail

--
To reply directly:
matusov at square peg ca
(join the domain name in one word and add a dot before "ca")
Reply to
MM

sorry for the delay, have been off work.

-- -------------------- RSTl

Reply to
Mike Nicklas

Mike,

Here is an example that works:

--------------------------------------------------

-- Entity Foo

-------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all;

entity foo is port ( ADIO: inout STD_LOGIC ); end foo;

architecture foo_behav of foo is begin

process begin ADIO

Reply to
MM

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