Driving INOUT signals

Can it be that you are initializing this signal in the test bench as zero? Assuming the signal is std_logic try setting it to 'L' or 'Z' instead.

/Mikhail

Hi

tried that too.

No joy unfortunately.

Any other ideas?

Regards

Mike

MM wrote:

Post the relevant pieces of your code... Are you saying it works in another simulator?

/Mikhail

Hi

here is a copy of the top module entity declaration. The testbench i tried was generated by a tool called HDL Bencher but i also tried using the command line interface on ModelSIM XE to no avail.

entity nueping2 is port ( -- Interface clock. DSP_CLK: in STD_LOGIC; -- Global reset. RSTl: in STD_LOGIC; -- Indicates whether Spartan can receive data. BUSY: in STD_LOGIC; -- Indicates whether Spartan has data to send. EMPTY: in STD_LOGIC; -- Indicates that ADIO is address or data. AS_DSl: in STD_LOGIC; -- Read/Write enable. RENl_WENl: out STD_LOGIC; -- Indicates if Spartan is being read or written to. RDl_WR: out STD_LOGIC; -- Interrupt to Spartan. INTl: out STD_LOGIC; -- Test LEDs. LEDS: out STD_LOGIC_VECTOR (7 downto 0); -- Data IO between Spartan and Virtex. ADIO: inout STD_LOGIC_VECTOR (31 downto 0) ); end nueping2;

I can add in the code from the auto-generated testbench as well if you like?

Mike

MM wrote:

This doesn't help much. We need to see how you drive the signal.

like?

Yes, but only the lines relevant to the signal of interest...

/Mikhail

sorry for the delay, have been off work.

-- -------------------- RSTl

Mike,

Here is an example that works:

--------------------------------------------------

-- Entity Foo

-------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all;

entity foo is port ( ADIO: inout STD_LOGIC ); end foo;

architecture foo_behav of foo is begin

process begin ADIO