Dear Sir or Madame,
I have the following VHDL code for the description of a RAM structure with some logic built around.
Why does QuartusII not synthesize it as a RAM structure using the memory bits of Cyclone?
Thank you for your help.
Kind regards
Andrés Vázquez G&D System Development
LIBRARY ieee; USE ieee.std_logic_1164.ALL;
PACKAGE test_ram_package IS
CONSTANT ram_width : INTEGER := 8; CONSTANT ram_depth : INTEGER := 2048; TYPE ram IS ARRAY(0 to ram_depth - 1) of std_logic_vector(ram_width-1 downto 0); SUBTYPE address_vector IS INTEGER RANGE 0 to ram_depth - 1;
CONSTANT xram_width : INTEGER := 11; CONSTANT xram_depth : INTEGER := 16; TYPE xram IS ARRAY(0 to xram_depth - 1) of std_logic_vector(xram_width-1 downto 0); SUBTYPE xaddress_vector IS INTEGER RANGE 0 to xram_depth - 1; END test_ram_package;
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; USE work.test_ram_package.ALL;
ENTITY test_inferred_ram IS PORT ( reset : IN std_logic; clock1 : IN std_logic; clock2 : IN std_logic; data : IN std_logic_vector(7 downto 0); write_address: IN address_vector; read_address: IN xaddress_vector; write_xaddress : IN xaddress_vector; xdata : IN std_logic_vector(10 downto 0); we : IN std_logic; q : OUT std_logic_vector(7 downto 0) ); END test_inferred_ram;
ARCHITECTURE rtl OF test_inferred_ram IS
SIGNAL ram_block : RAM; SIGNAL xram_block : XRAM; SIGNAL read_address_reg : xaddress_vector; SIGNAL writing : std_logic; BEGIN
PROCESS(clock1, reset) BEGIN IF reset='1' then writing