I havw writtent the following code. It compiles correctly. When i run the simulation it just stops and points to this statement variable result : unsigned(bw-1 downto 0);
The code and test bench are as below
-- VHDL library declarations library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all;
-- entity declaration entity floor_top is generic ( bwin : integer:= 6; bwout : integer := 3); port( x : IN unsigned(bwin-1 downto 0); bw : IN integer; y : OUT unsigned(bwout-1 downto 0) ); END floor_top;
-- architecture declaration architecture behavioral of floor_top is
-- function declaration function floor( x: unsigned; bw: integer) return unsigned is variable result : unsigned(bw-1 downto 0); begin result := resize(x,bw); return result; end floor;
begin
yLIBRARY IEEE; USE IEEE.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all;
ENTITY util_tb IS -- testbench entity is ALWAYS EMPTY END util_tb;
ARCHITECTURE tb OF util_tb IS
-- local signal declaration SIGNAL x : unsigned(5 downto 0) ; SIGNAL bw : integer; SIGNAL y : unsigned(2 DOWNTO 0);
-- component declaration COMPONENT floor_top IS generic ( bwin : integer:= 6; bwout : integer := 3); port( x : IN unsigned(bwin-1 downto 0); bw : IN integer; y : OUT unsigned(bwout-1 downto 0) ); END COMPONENT;
BEGIN UUT : floor_top PORT MAP( x => x, bw => bw, y => y );
-- apply inputs to monitor outputs x