simulation problems

I havw writtent the following code. It compiles correctly. When i run the simulation it just stops and points to this statement variable result : unsigned(bw-1 downto 0);

The code and test bench are as below

-- VHDL library declarations library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all;

-- entity declaration entity floor_top is generic ( bwin : integer:= 6; bwout : integer := 3); port( x : IN unsigned(bwin-1 downto 0); bw : IN integer; y : OUT unsigned(bwout-1 downto 0) ); END floor_top;

-- architecture declaration architecture behavioral of floor_top is

-- function declaration function floor( x: unsigned; bw: integer) return unsigned is variable result : unsigned(bw-1 downto 0); begin result := resize(x,bw); return result; end floor;

begin

y

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all;

ENTITY util_tb IS -- testbench entity is ALWAYS EMPTY END util_tb;

ARCHITECTURE tb OF util_tb IS

-- local signal declaration SIGNAL x : unsigned(5 downto 0) ; SIGNAL bw : integer; SIGNAL y : unsigned(2 DOWNTO 0);

-- component declaration COMPONENT floor_top IS generic ( bwin : integer:= 6; bwout : integer := 3); port( x : IN unsigned(bwin-1 downto 0); bw : IN integer; y : OUT unsigned(bwout-1 downto 0) ); END COMPONENT;

BEGIN UUT : floor_top PORT MAP( x => x, bw => bw, y => y );

-- apply inputs to monitor outputs x

Reply to
FPGA
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The error i get is as follows # ** Fatal: (vsim-3965) Memory Allocation is too large. Please check your usage. # Time: 0 ns Iteration: 0 Process: /util_tb/uut/line__55 File: C:/ Modeltech_pe_edu_6.3c/examples/floor_top.vhd # Fatal error in Subprogram floor at C:/Modeltech_pe_edu_6.3c/examples/ floor_top.vhd line 47

line 47 in my code is variable result : unsigned(bw-1 downto 0);

Reply to
FPGA

Reply to
Tricky

It would.

This is NOT a standard library. Don't use it.

This is a standard library and works well.

What you have done here is introduce two different incompatible definitions of "unsigned"...

- Brian

Reply to
Brian Drummond

I fixed the problem which I had initially. I have a new one now :)

** Fatal: (vsim-3420) Array lengths do not match. Left is 3 (2 downto 0). Right is 0 (-1 downto 0 (null array)). # Time: 0 ns Iteration: 0 Process: /util_tb/uut/line__55 File: C:/ Modeltech_pe_edu_6.3c/examples/floor_top.vhd # Fatal error in Architecture behavioral at C:/Modeltech_pe_edu_6.3c/ examples/floor_top.vhd line 55 #

l>

Reply to
FPGA

For some reason, and I'm not sure why yet, bw is starting out at zero. The earlier comments about the assignment taking place at 0 + 1 or more deltas is correct, but as per the previous comment, I would have expected the initial value on bw to be integer'low which is at least -(2**31-1).

There are a couple of ways to fix the problem, the simplest it to explicitly initialize bw to 3 in its declaration.

However, the bw parameter shouldn't really be associated with a signal or even a variable, since it sets the width of the return value, and that must match the static width of the signal to which the result is being assigned. Therefore, bw should probably be a constant, or could also be replaced by y'length in the call to floor.

I would also declare the bw constant to be of type positive, since you know it has to be greater than zero. If it were a generic, I would certainly declare it with type positive to ensure that nobody tried to set it to zero or negative.

On the subject of generics, I noticed the comment in your code that test bench entities are ALWAYS EMPTY. Such is not the case. It can be very useful to put generic declarations on the test bench entity, with default values, so that they can be overridden via command-line option when compiled/elaborated/simulated. This can be used to run different test cases without changing the code.

Hope this helps,

Andy

Reply to
Andy

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