1. Home
  2. Field-Programmable Gate Arrays
  3. Modulation Clock to set FPGA timing

Modulation Clock to set FPGA timing

I am looking for some help in regards to a 20 MHz modulation clock that needs to set the timing in the Virtex_II_Pro. I was investigating running the modulation clock into a DCM; However, the minimum input frecquency for CLKIN is 24MHz. The 20 MHz modulation clock needs to establish the timing in the FPGA for synchronizing the 80MHz ADC and for digital mixing of the modulation frequency. If I can not use a DCM, how do I create the synchronous timing for my subsystems 80MHz and digital mixing?

Reply to
cyd
Loading thread data ...

Hi Cyd, I confess I have never used a V2 Pro but looking in the datasheet the DCM supports the frequency synthesizer which can output a multiplied clock on CLKFX. If you are not using the DLL then the minimum input clock is 1MHz, not 24MHz. (the 24MHz spec applies when using the DLL).

Perhaps also read the Xilinx application note XAPP462. I found it easy to read and it answered all my questions. XAPP462 is for the spartan 3 DCM though...probably there is an equivalent app note for the V2 Pro DCM....

Regards Andrew

cyd wrote:

Reply to
Andrew FPGA

Andrew, Thanks for the great tips, I did see the same minimum frequency for the DCM when not using the DLL feature, and read some of the XAPP462. I think this should get me rolling.

cy

Reply to
cyd

Hi Cyd, I suggest you read the clock jitter specs for your ADC carefully. Clock jitter raises the noise floor, since the ADC converts timing noise into amplitude noise. Peter Alfke

Reply to
Peter Alfke

Dear Cyd,

There are two issues you would have to address.

(*) You are able to generate 80 MHz out of 20, if you use CLKFX output ONLY, as the minimum frequency for this case is 1 MHz. I did this. It's working. (**) Using CLKFX implies that you would have some jitter induced by frequency synthesizer as per its tapped delay line's nature.

Vladislav

Reply to
Vladislav Muravin

Peter,

It has been awhile, It took awhile but have understood your concern good advice. Some of my best case jitter has been an order of magnitude better than the worst case scenarios given app notes and the DCM wizard. I write because I wanted to confirm that this is not the case for the buufered output of the DCM, namely, CLKIN_IBUFG_OUT. This is merely a input clock buffer, used for high clock fan out, as I understand it. My question, Peter, is there any jitter attached to the ibufg componenet, and using this output from the DCM is not constrained by the DCM jitter problem, right?

thans

Cy

Reply to
cyd

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.