Hi.
I have a design target to xilinx virtex2pro30 device. In the map stage I get "ERROR:342 design does not fit in device".
But although I run "map -detail", the tool does not give me any details such as how far I am off the device limitation, in what category my design does not fit (registers or luts) etc ...
Is there a way to extract this information from the Xilinx ISE tools ?
ThankX, NAHUM
schrieb im Newsbeitrag news: snipped-for-privacy@f14g2000cwb.googlegroups.com...
Are you sure? Usually it clearly says what kind of component is over thelimit (LUTs, Slices, BRAMS, BUFGs etc.) Have a closer look again.
Regards Falk
MAP report file (*.mrp) is the place usually to look for the resources used.
John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.
OK.
It seems that only when you run 'map' with '-timing' option, there is no area report when the design does not fit in device.
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