Quartus SignalTap (and ISE equivalent ChipScope) are a truly awesome tools, however I ran into something strange.
As part of my design I interface an SRAM (this is the Nios Dev kit, Cyclone Ed.), and thus have a net like
module main(... inout wire [31:0] fse_d, output reg sram_oe_n, ...
reg [31:0] fse_d_out; assign fse_d = sram_oe_n ? fse_d_out : 32'hZZZZZZZZ; ....
but in the captured data fse_d is shown changing one cycle after fse_d_out. Is this delay an expected bus turn around associated with a tristate bus?
Just to be sure I understood this correctly, I added an
wire [7:0] fse_d_out_plus_1 = fse_d_out + 1;
and it does show up as expected, synchronous with fse_d_out, in the trace.
BTW everything, including SignalTap, is synchronized to the same 200 MHz clock synthesized with a PLL.
Thanks