Puzzled Simulating with 'X' input Quartus II v4.0 sp1

I was simulating with some inputs set to 'X'=unknown on the inputs and observing defined outputs where I thought the output should be indeterminate. Playing around some, I've reduced things to the following example. The outputs are as determined by QuartusII v4.0SP1. No optimizations turned on. The logic is not inside a process, but that doesn't make a difference. Quartus II v3.0 sp2 behaves exactly the same.

A,B,Sel : in std_logic; Y,Z : out std_logic;

-- Straight Combinatorial Logic:

Y Y Z 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 1 1 1 1 so far so good !

X 0 0 0 0 X 0 1 0 U :-( why is Y==A when Sel='X' ?? X 1 0 1 U X 1 1 1 U ! simulator is able to figure out Z=0 when A=B=0 but isn't able to figure out the case A=B=1 X X 0 X U X X 1 X U ok no surprises here...

X 0 X 0 U X 1 X 1 U well its consistent...

X X X 0 U @#$% Zero ???

So here's my questions...

(1) Is it a bad idea to use 'X' in a simulation ?

(2) Is there something I'm missing that explains this behavior ?

(3) I tried other logic functions and all possible 2-input combinations with

9-valued inputs. The mux is the only thing that I find puzzling. Is there a preferred way to write the mux ?

P.S.:

1.As one might expect, the following behaves the same as the above expr for Y

process (A,B,Sel) begin if Sel='1' then Y

Reply to
Rajeev
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Hi Rajeev,

The Quartus simulator is not a behavioral simulator. It simulates a synthesized circuit which is functionally equivalent to the users specification. The synthesizer is free to assign an 'X' signal to either 1 or 0 to reduce the logic.

Hope this helps.

- Subroto

Reply to
Subroto Datta

Subroto,

Thank you for taking the time to respond. I'm not sure what to conclude from your email however.

Let me mention a few things...

a. There is no 'X' value in the design. The synthesizer never sees an 'X'. The 'X' is a simulation input (and output) only.

b. I'm afraid I cannot see what synthesized circuit is equivalent to my specification but gives output=0 for all 3 inputs = 'X'.

c. In v4.0 (I should look in 3.0 also) the synthesis results in a _single_ equation that is fed to both outputs Y and Z. That equation is

A1L7 = A & (B # Sel) # !A & B & !Sel; Y = OUTPUT(A1L7); Z = OUTPUT(A1L7);

Yet Y and Z simulate differently ! So, what is the simulator simulating ?

Incidentally I can't help being curious why the synthesizer prefers this form to

A1L7 = A & Sel # B & !Sel;

Regards,

-rajeev-

Reply to
Rajeev

0 AND anything is always 0. But 1 AND X is not 1. So the OR of two unknowns is not a known. The value of X is not the same as "don't care" or not sure if it is a 0 or a 1. It can also be hi-z and will result in an unknown state on the output of the AND gate.

It would seem X is not a useful state in this simulator. In a proper VHDL simulator X has a defined behavior and is the default for FFs that are not init'd or inputs that are not assigned.

Try using a proper VHDL simulator. I use the Xilinx version of Modelsim.

Is this simulation *after* synthesis? If so I have no idea why your two results would be different. I read your later message and you show the two outputs use the same equation, but your simulation gives different results. It *must* be simulating before synthesis.

--
Rick "rickman" Collins

rick.collins@XYarius.com
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Reply to
rickman

To be a bit more specific, 'U' is the undefined or "start-up" state. 'X' is what appears when you drive two clashing values onto a std_logic. Or when the simulator sees a D input change inside the setup-hold window of a FF.

I've never used an 'X' in simulation - created a few inadvertently though...

If you want a "don't-care" use '-' instead.

Cheers, Martin

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martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
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Reply to
Martin Thompson

Your point about HiZ is well taken. I had been using 'X' mentally thinking of it as "could be either 0 or 1".

I fully acknowledge the need to move to a different simulator. My present project has been marching through the design steps, and there's not been a stage where I've been willing to invest the time to learn to use ModelSim.

While I have a ModelSim-Xilinx, it would be more straightforward to use the ModelSim-Altera - in particular I anticipate it would be straighforward to feed it Altera specific megafunctions (for example I tend to use lpm_count after having Quartus not infer a couple of counters - perhaps I should have put in more effort understanding how to write the counter so it _would_ be inferred). Though I seem to recall people mentioning in the group that ModelSim-Xilinx offers a more complete feature set. Have you used ModelSim-Altera, and if so has your experience been satisfactory ?

Now that's a mighty interesting question. In the original post I'd given an example from QII v4.0sp1 where 2 expressions (that synthesize the same) give different simulation results, so it sure doesn't appear to be simulating what it's synthesizing. On the other hand, it does force you to execute a step called "Generate Functional Simulation Netlist" before doing the simulation. As I look at it, a netlist is kind of like a wiring list, ie what to connect to what... but you have to know what are the pieces (gates ?)you're connecting in order to simulate -- and that sounds like synthesis to me.

The story with QII v3.0sp2 is a little different. I didn't have the "check outputs" checkbox enabled when I ran it, so I must amend an earlier post where I said the results are exactly the same as v4.0sp1. >

Also, Stratix MegaRAM cannot be initialized. When I inspect the contents in the Quartus v4.0 simulator it is full of 'X'.

I had imagined '-' as something to be specified on an output that would match any of the other 8 values. I guess I need to study the definitions and usage of these other states.

I can see that there are a few things to explore, let me report back perhaps in a couple of weeks.

Thanks,

-rajeev-

Reply to
Rajeev

Ahh, I may have missed the fact you were using the Quartus simulator - that may or may not be VHDL-compliant in its usage of these symbols - my comments were aimed purely from the VHDl point of view.

If the Quartus memory model is full of X in a VHDL simulation, that's because the model has 'initialised them' that way, the VHDL simulator will put U everywhere until told otherwise...

That is the case in VHDL, sort of. Don't know about Quartus.

I say sort of, because if you compare two std_logics using the "=" operator, a '-' will only match a '-', so it won;t act the way you might expect. To do that you have to use (IIRC) std_match from the numeric_std library. See here for more details:

formatting link

This is VHDl, though - not knowing anything else about the Quartus built-in simulator, I'd better shut up now!

Cheers, Martin

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martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
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Reply to
Martin Thompson

The Quartus simulator uses waveforms on the netlist. It can't handle any HDL.

-- Mike Treseler

Reply to
Mike Treseler

Hello Rajeev,

My apologies for not asking you first whether you were using the builtin Quartus II simulator or an external simulator. The Quartus II simulator in versions 4.1 and earlier ignores 'X' events on the select signal of a mux. This is a bug and will be fixed in Quartus II 4.2.

To work around this problem you wil need to do a timing (aka post-layout simulation). The post-layout netlist is written using VHDL and Verilog library models which support the 'X' behavior correctly. You will need access to a VHDL/Verilog simulator like the Modelsim or NC-Sim among others.

- Subroto Datta Altera Corp.

Reply to
Subroto Datta

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