I was simulating with some inputs set to 'X'=unknown on the inputs and observing defined outputs where I thought the output should be indeterminate. Playing around some, I've reduced things to the following example. The outputs are as determined by QuartusII v4.0SP1. No optimizations turned on. The logic is not inside a process, but that doesn't make a difference. Quartus II v3.0 sp2 behaves exactly the same.
A,B,Sel : in std_logic; Y,Z : out std_logic;
-- Straight Combinatorial Logic:
Y Y Z 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 1 1 1 1 so far so good !
X 0 0 0 0 X 0 1 0 U :-( why is Y==A when Sel='X' ?? X 1 0 1 U X 1 1 1 U ! simulator is able to figure out Z=0 when A=B=0 but isn't able to figure out the case A=B=1 X X 0 X U X X 1 X U ok no surprises here...
X 0 X 0 U X 1 X 1 U well its consistent...
X X X 0 U @#$% Zero ???
So here's my questions...
(1) Is it a bad idea to use 'X' in a simulation ?
(2) Is there something I'm missing that explains this behavior ?
(3) I tried other logic functions and all possible 2-input combinations with
9-valued inputs. The mux is the only thing that I find puzzling. Is there a preferred way to write the mux ?P.S.:
1.As one might expect, the following behaves the same as the above expr for Yprocess (A,B,Sel) begin if Sel='1' then Y