Xilinx DDR output with tri-state....

I found an answer, and here's the code to implement byte-wide bi-directional DDR pins. I believe part of the magic it took to make this work was to a) keep hierarchy b) pass the tri-state enable signals as an 8 bit bus so that XST doesn't optimize them into a single signal. c) use 8 copies of the tri-state 'assign'

// DDR_TRI // This module provides a BYTE wide, Bi-directional DDR pad interface with // tri-state flip-flop embedded in the IOB. // // NOTEs: // a) you need to bring in 8 copies of the tri-state control signal so // that XST doesn't optimize the tri_q signals improperly // // b) you must use 8 of the // assign foo[x] = enable[x] ? 1'bz : q[x]; // if you try to use // assign foo = enable ? 8'bz : q; // the tri-state control flip-flop doesn't get packed into the IOB // module ddr_tri( clk_out, clk_out_n, clk_in, clk_in_n, data_out_even, data_out_odd, data_in_even, data_in_odd, tri_ctl, dq ); input clk_out; input clk_out_n; input clk_in; input clk_in_n; input [7:0] data_out_even; input [7:0] data_out_odd; output [7:0] data_in_even; output [7:0] data_in_odd; input [7:0] tri_ctl; inout [7:0] dq;

reg [7:0] data_in_even; reg [7:0] data_in_odd; reg [7:0] tri_q; wire [7:0] fddq;

//synthesis attribute IOB of tri_q is "TRUE" always @(posedge clk_out_n) tri_q targeted at a V2-Pro part.