currently I am working on a small hobby project with the Spartan 3 Starter Kit board from Xilinx. I use ISE WebPack 8.1i and Verilog as a language.
Now some questions have come up during this:1) There is a need to implement bus structures, say a 16 bit bidirectional data bus which should connect several modules on the highest level of the project.
1a) Do i understand it right that although there is an "inout" statement for pins in verilog, this is of no use here, as it is working fully only for IO-Pins on the main level, which connect to physical pins of the FPGA itself ?1b) Additionally there seems to be no possibility (at least for the Spartan 3 device) that several outputs from different modules drive a single bus line, even if care is taken for a proper assignment of 1'bz values.
So the consequence seems to be the following (my own thought): if one has modules
m1, m2, m3
and one is intending
m1(inout d), m2(inout d), m3(inout d)
one has in reality to do
m1(in din, out d1), m2(in din, out d2), m3(in din, out d2)
and declare a 4th module
bus_star(in sd1, in sd2, in sd3, out sdo)
sdx to dx (x from 1 to 3) din to sdo
The 4th module I called "bus_star" as it is internally realising a star shaped topology on the buses, wire-oring the products
(sdi and eni)
to give sdo. The signals eni here are enable signals, which dictate which of the modules mx is allowed to "talk out" over dx into the sdo and therefore into the din bus.
Is this correctly thought ? Or is there an easier way ?1c) If the way in 1b) is correct, can the duplication of the buses (d1, d2, d3) - which are in reality maybe 32 bit wide - lead to practical problems in routing on the FPGA chip ? (Too many lines ?)
2) A second, totally unrelated question: Is there a verilog simulation module for the static RAMs on board of Spartan3 Starter Kit ? I intend to write a synchronous RAM-controller for these asynchronous RAMs and would like to test it before, possibly, damaging the RAMs with wrong code. (Or is this impossible ?)