I have a question concerning the VHDL description of a bidirectional bus.
This bus comes from (goes to) an SRAM which I try to simulate with a corresponding VHDL model.
Now I have an INOUT pin at my SRAM-Controller : Sram_data : inout(7 downto 0);
Within my SRAM-Controller I have the local signals l_sram_data_out : std_logic_vector(7 downto 0); l_sram_data_in : std_logic_vector(7 downto 0);
l_sram_data_out describes the data which I want to write into the SRAM. l_sram_data_out is a registered signal.
l_sram_data_in describes the data I want to read from the SRAM.
The signal which is responsible for writing to the SRAM or reading out of the SRAM is WE_bar. WE_bar='0' & CS_bar='0' & OE_bar='1' ---> Write to the SRAM WE_bar='1' & CS_bar='0' & OE_bar='0' ---> Read from the SRAM
How can I connect l_sram_data_out and l_sram_data_in in a appropriate way to the bidirectional bus?
Does l_sram_data_in has to be synchronized? (It is used within the controller in a synchronous environment)
I would appreciate any helpful hint.
Kind regards André V.