Hi
I have problems instantiating the ramb4_s1_s16 in vhdl. ramb4_s2_s16 works fine. The error message is ... =========================================================================
- Low Level Synthesis * ========================================================================= ERROR:Xst:79 - Model 'RAMB4_S1_S16' has different characteristics in destination library ERROR:Xst:1831 - Missing ports are:DOA0 DIA0 ERROR:Xst:1832 - Unknown ports are:DOA DIA ERROR: XST failed Process "Synthesize" did not complete.
Following I have listed my test code for both blockrams. Can anybody show me what I missed?
Frank
///////////////////////////////////////////////////////////////////////////// library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity testram2 is port ( DOA : out STD_LOGIC_VECTOR (0 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0); ADDRA : in STD_LOGIC_VECTOR (11 downto 0); ADDRB : in STD_LOGIC_VECTOR (7 downto 0); CLKA : in STD_ULOGIC; CLKB : in STD_ULOGIC; DIA : in STD_LOGIC_VECTOR (0 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); ENA : in STD_ULOGIC; ENB : in STD_ULOGIC; RSTA : in STD_ULOGIC; RSTB : in STD_ULOGIC; WEA : in STD_ULOGIC; WEB : in STD_ULOGIC ); end testram2;
architecture Behavioral of testram2 is component RAMB4_S1_S16 port ( DOA : out STD_LOGIC_VECTOR (0 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0); ADDRA : in STD_LOGIC_VECTOR (11 downto 0); ADDRB : in STD_LOGIC_VECTOR (7 downto 0); CLKA : in STD_ULOGIC; CLKB : in STD_ULOGIC; DIA : in STD_LOGIC_VECTOR (0 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); ENA : in STD_ULOGIC; ENB : in STD_ULOGIC; RSTA : in STD_ULOGIC; RSTB : in STD_ULOGIC; WEA : in STD_ULOGIC; WEB : in STD_ULOGIC ); end component;
begin ram0 : RAMB4_S1_S16 port map( CLKA => CLKA, WEA => WEA, ADDRA => ADDRA, DIA => DIA, DOA => DOA, ENA => ENA, RSTA => RSTA, CLKB => CLKB, WEB => WEB, ADDRB => ADDRB, DIB => DIB, DOB => DOB, ENB => ENB, RSTB => RSTB );
end Behavioral; ///////////////////////////////////////////////////////////////
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity testram is port ( DOA : out STD_LOGIC_VECTOR (1 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0); ADDRA : in STD_LOGIC_VECTOR (10 downto 0); ADDRB : in STD_LOGIC_VECTOR (7 downto 0); CLKA : in STD_ULOGIC; CLKB : in STD_ULOGIC; DIA : in STD_LOGIC_VECTOR (1 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); ENA : in STD_ULOGIC; ENB : in STD_ULOGIC; RSTA : in STD_ULOGIC; RSTB : in STD_ULOGIC; WEA : in STD_ULOGIC; WEB : in STD_ULOGIC ); end testram;
architecture Behavioral of testram is component RAMB4_S2_S16 port ( DOA : out STD_LOGIC_VECTOR (1 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0); ADDRA : in STD_LOGIC_VECTOR (10 downto 0); ADDRB : in STD_LOGIC_VECTOR (7 downto 0); CLKA : in STD_ULOGIC; CLKB : in STD_ULOGIC; DIA : in STD_LOGIC_VECTOR (1 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); ENA : in STD_ULOGIC; ENB : in STD_ULOGIC; RSTA : in STD_ULOGIC; RSTB : in STD_ULOGIC; WEA : in STD_ULOGIC; WEB : in STD_ULOGIC ); end component; begin
ram0 : RAMB4_S2_S16 port map( CLKA => CLKA, WEA => WEA, ADDRA => ADDRA, DIA => DIA, DOA => DOA, ENA => ENA, RSTA => RSTA, CLKB => CLKB, WEB => WEB, ADDRB => ADDRB, DIB => DIB, DOB => DOB, ENB => ENB, RSTB => RSTB );
end Behavioral;