Initialize Blockram from file

You can certainly do it using Core Gen. Also, if you look under language templates in Project Navigator, you can do it with defparams:

// RAMB16_S1: Virtex-II/II-Pro, Spartan-3 16kx1 Single-Port RAM // Xilinx HDL Language Template version 6.1i

RAMB16_S1 RAMB16_S1_inst ( .DO(DO), // 1-bit Data Output .ADDR(ADDR), // 14-bit Address Input .CLK(CLK), // Clock .DI(DI), // 1-bit Data Input .EN(EN), // RAM Enable Input .SSR(SSR), // Synchronous Set/Reset Input .WE(WE) // Write Enable Input );

// The following defparam declarations are only necessary if you wish to change the default behavior // of the RAM. If the instance name is changed, these defparams need to be updated accordingly.

defparam RAMB16_S1_inst.INIT = 1'h0; // Value of output RAM registers at startup defparam RAMB16_S1_inst.SRVAL = 1'h0; // Ouput value upon SSR assertion defparam RAMB16_S1_inst.WRITE_MODE = "WRITE_FIRST"; // WRITE_FIRST, READ_FIRST or NO_CHANGE

// The following defparam INIT_xx declarations are only necessary if you wish to change the initial // contents of the RAM to anything other than all zero's.

defparam RAMB16_S1_inst.INIT_00 =

256'h0000000000000000000000000000000000000000000000000000000000000000; Cheers, JonB

I think you're looking for a way to initialize the RAM after the FPGA is placed and routed so you don't need to recompile? If you use the .ucf file to initialize the RAM it will require re-running place-and-route. There is an article on merging RAM data directly into the bitstream file in the TechXclusives section of Xilinx.com titled "Reconfiguring Block RAMs" by Kris Chaplin

You can initialize BlockRAM after the bitfile has been created using a tools called Data2MEM that is part of the Xilinx ISE tools. To read more about Data2MEM goto:

Shal> I think you're looking for a way to initialize the RAM after