Inferring Xilinx BlockRAM FIFO

The Xilinx built-in blockRAM FIFOs seem pretty nice, but is there any way t o infer them? Probably not. They're not that useful otherwise, unless you want to instantiate the primitive (not really), use CoreGen (no), and simu late using a unisim (who's got the time?).

I always thought it'd be nice if Synplify could infer the Systemverilog pus h_front and pop_back queue commands as a FIFO and then use its own SynCore tool to make a FIFO from that. I might have to wait another 7-8 years for that one.

Reply to
Kevin Neilson
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In Vivado you can script IP generation. You might be able to generate a FIFO on the fly prior to the actual synthesis. Check the Vivado documentation.

It might also be possible to script the Synplify SYNCore FIFO Wizard from TCL even though I never tried.

Synplify Premier has support for DesignWare where you can "infer" (or more like parametrized instantiation) complex components. However, I don't know if the DW_fifo_2c_df will map into the Xilinx block-RAM FIFO's.

:-) I guess most Synthesis tools would tell you that the queues are only supported for simulation.


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Reply to
Petter Gustad







Yes, just create your own FIFO in Verilog or VHDL. I have done this and XST will create a BRAM FIFO for you.


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Did the synthesis tool infer a BRAM addressed by your own index counters, or did it infer a FIFO hard macro, using the built-in address HW in the FIFO?

The OP was seeking the latter.

I have not seen any synthesis tools automatically employ built-in FIFO address HW for RTL-described indexing counters and full/empty logic.


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