Inferring Xilinx BlockRAM FIFO

In Vivado you can script IP generation. You might be able to generate a FIFO on the fly prior to the actual synthesis. Check the Vivado documentation.

It might also be possible to script the Synplify SYNCore FIFO Wizard from TCL even though I never tried.

Synplify Premier has support for DesignWare where you can "infer" (or more like parametrized instantiation) complex components. However, I don't know if the DW_fifo_2c_df will map into the Xilinx block-RAM FIFO's.

:-) I guess most Synthesis tools would tell you that the queues are only supported for simulation.

//Petter

t=

you=

simu=

pus=

Yes, just create your own FIFO in Verilog or VHDL. I have done this and XST will create a BRAM FIFO for you.

Jon

--------------------------------------- Posted through

Jon,

Did the synthesis tool infer a BRAM addressed by your own index counters, or did it infer a FIFO hard macro, using the built-in address HW in the FIFO?

The OP was seeking the latter.

I have not seen any synthesis tools automatically employ built-in FIFO address HW for RTL-described indexing counters and full/empty logic.

Andy