The Xilinx built-in blockRAM FIFOs seem pretty nice, but is there any way t o infer them? Probably not. They're not that useful otherwise, unless you want to instantiate the primitive (not really), use CoreGen (no), and simu late using a unisim (who's got the time?).
I always thought it'd be nice if Synplify could infer the Systemverilog pus h_front and pop_back queue commands as a FIFO and then use its own SynCore tool to make a FIFO from that. I might have to wait another 7-8 years for that one.