I'm about to use an APA1000 with Actels implementation of dual port RAMs. These require the use of the PLL to create a X2 clock.
My input clock is 33MHz, but this goes to another FPGA as well, and the skew between the two chips must be kept to a minimum. So, will the PLL output of 66MHz have its rising edges coincident with the edges of the 33MHz clock?
Anyone had experience of using these PLLs, good or bad.
Regards, Niv.