Global signal conservation

David Ashley wrote: [...]

Yep.

Could you name the parts you are referring to? I find it surprising that an inverter within the global clock network would take that long, and more surprising that you can get off the global clock net and through a LUT-based inverter. So surprised, in fact, that I had to go try it for myself. I put three different examples in the design, rising_edge(clk), falling_edge(clk) as well as a clk_inv So perhaps it's a tradeoff -- minimum skew requires

Don't forget the skew between different global clock nets caused by uneven loading of the clocks (if some have much heavier loading than others).

Yes. These things, and many others :-)

Have fun,

Marc

This is the spartan-3e series. I had just assumed the LUT would be involved in inverting a clock.

I'm looking at the spartan-3e family data sheet, and I have the diagram for the CLB up. On the right side are FFX and FFY and these are only clocked by a single CK line, and there is no option for inverting it. Are you talking about inverting the signal or the clock?

There is a note on page 22 of ds312-spartan-3e-family.pdf 1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown.

I spent some time looking but didn't find any optional inverter on the clock.

Hmmm. That rising_edge() vs falling_edge() issue is interesting. The design I'm studying uses unisim fddrrse entities. These expect 2 clocks -- true and inverted. But the vhdl for the entity could be rewritten to take a single clock, but just use rising_edge and falling_edge in its implementation. Xilinx didn't do this.

So this brings up a question -- would it be better coding practice to make use of rising_edge/falling_edge, or instead use 2 clocks? Unisim seems to opt for the 2nd option. Is compatibility with unisim important? In fact the things in unisim that are used by the designs I'm studying (opencores ddr controller for example) are trivial -- having unisim even involved doesn't really buy anything. And unisim I think is xilinx specific.

-Dave

David, when we say that something "is not shown", it means that we uncluttered the drawing by not showing something (that really is there). No wonder you could not find it in the schematic, it "is not shown" The conditional inverter is usually some kind of XOR circuit, carefully balanced, so that it does not affect the through-delay. Peter Alfke

Peter,

Very good info. BTW is there any mention of the optional inverter on the CK input in the datasheet? If this is a word-of-mouth type of tidbit I'm worried about what *else* I need to learn this way :^).

Anyway this clears up the whole question I had. Just because the DCM outputs an inverted clock doesn't mean you gain any advantage by using it -- because the CLB's can use the true clock or inverted and there is no penalty. This is really good stuff I need to know but didn't.

Thanks all,

-Dave

When using Xilinx, the best way to see what hardware is actually there is to use fpga_editor. You don't even need a design; just create a new one, make up a name, and select the part you want to look at. Then you can double-click on the slice and see what is inside of it.

Alan Nishioka

Rebooted into windows and launched fpga_editor, and was able to see the detail, sure enough there's an inverter right there. Thanks for the tip.

Tried launching fpga_editor from linux but it doesn't work.

dave% /Xilinx/bin/lin/fpga_editor Cannot register service: RPC: Unable to receive; errno = Connection refused unable to register (registryProg, registryVers, tcp)

-Dave