Good morning every body, I'm working with an APEX 20K600E -2x and have a trouble with the embedded clocks PLLs, and I need help:
With my 40 MHz system-clock I drive a Double Data Rate output, which is implemented by Synplify with a multiplexer, the clock beeing the selection pin: msb on the high level, lsb on the low level,. That is a usual, and works fine with an external global clock.
In order to lower the tco time (horrible 9ns!), I tried to use the embedded PLLs to create an internal clock with an advanced phase, and then Quartus refuses to connect the Clock to the multiplexer selection pin:
"Error: ClockLock pll ...... must drive only a pin or clock port."
Is there any solution to implement a Double Data Rate output with a PLL generated clock??
Thank you in advance,
Pierre-Louis