Anyone ever seen the contents of an FPGA "rom" (made up of several Stratix M4k rams with one read only port) corrupted?
I have a design where the 80 mhz system clock is coming via the sample clock in-out path of a high performance ADC from an external low phase noise generator. If the clock glitches, cuts out, etc, the contents of some, but not all, of my FIR coefficient ROMs get scrambled.
The read ports of these ROMs are run from this clock, but it shouldn't be possible to write to them. I also have a RAM that is writeable, and it similarly gets scrambled.
I don't really want to use the clock PLLs, since my output registers need to be synchronized to the low phase noise source, which an FPGA PLL is not. I did some preliminary experiments with clocking most of the logic from a PLL and keeping only the input and output registers on the raw clock input, but I don't like working around a problem that in my opinion really shouldn't be happening.
Any ideas why clock glitches could corrupt the ROMs? Only theory I can come up with is that maybe a bunch of faster than usual edges kerchunk all the logic, overtaxing the instantaneous power supply.
Anyone seen something similar?