I was a TA for an introductory VHDL lab yesterday and I encountered a very weird problem. In the source code included below I get the following interesting messages from XST when I try to synthesize the file:
INFO:Xst:1799 - State start is never reached in FSM . INFO:Xst:1799 - State stop is never reached in FSM . INFO:Xst:1799 - State data_1 is never reached in FSM . INFO:Xst:1799 - State data_2 is never reached in FSM . INFO:Xst:1799 - State data_3 is never reached in FSM . INFO:Xst:1799 - State data_4 is never reached in FSM .
and
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
Personally I cannot see any reason why stage shouldn't leave the waiting state. On the other hand I might just have missed something blindingly obvious. If I simulate the design in ModelSim it does leave the waiting state immediately. I don't get any such messages if I try to synthesize to for example a Virtex 4.
The sad thing is that this is the first time the students were exposed to Xilinx tools and VHDL and I fear that the first impression wasn't very good :(
In ISE 7.1, 8.1, and 9.1 for Linux xst gives the same warnings. ISE 6.3 for Solaris does not emit any warning however.
8.1 for Windows also gives the warnings about the timer but I haven't double checked that they give the same INFOs for the stage signal.Do we have to go back to ISE 6.3 to have functioning XC9536 support?
I guess this posting is mainly a way to vent some irritation, but I do hope that someone at Xilinx sees this because the last time I tried to report a possible bug to Xilinx my request for a webcase account was denied. (At that time they referred me to the University program forums and I never got any useful reply to my message.)
/Andreas
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-- The following code has been modified somewhat
-- by removing as much stuff as possible while still
-- retaining the problematic code.
------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity transmitter is port( clk: in std_logic; reset: in std_logic; debug:out std_logic_vector(1 downto 0)); end transmitter;
architecture arch of transmitter is type state is (waiting, start, data_1, data_2, data_3, data_4, stop); signal stage: state; signal timer: std_logic_vector(3 downto 0); begin
process(clk) begin if rising_edge(clk) then timer