Hi,
I am designing with Virtex 4, which needs DCM output clk0/90/180/270 at more than 300MHz. I use a ibufg to connects the fpga input clock and connects ibufg output to DCM input directly. Then I set this constraint with period 3.2ns. I output clk0/clk90/clk180/clk270 with bufg. Unfortunately I failed timing. I checked with Timing Analyzer and got such information:
================================================================================ Timing constraint: TS_clk_90_in = PERIOD TIMEGRP "clk_90_in" TS_clk_ibufg_out PHASE 0.8 ns HIGH 50%;
2 items analyzed, 1 timing error detected. (1 setup error, 0 hold errors) Minimum period is 4.972ns.
-------------------------------------------------------------------------------- Slack: -0.443ns (requirement - (data path - clock path skew + uncertainty)) Source: u_datarecovery_a6_i/FF0 (FF) Destination: u_datarecovery_c5_i (FF) Requirement: 0.800ns Data Path Delay: 1.040ns (Levels of Logic = 0) Clock Path Skew: -0.003ns Source Clock: clk_180 rising at 0.000ns Destination Clock: clk_90 rising at 0.800ns Clock Uncertainty: 0.200ns
I am confused by the slack: (requirement - (data path - clock path skew
- uncertainty)), Can any body help me to explain this? And how to reduce this data path dealy? Seems my design fails with this.
for anothe path, I got:
-------------------------------------------------------------------------------- Slack: 1.399ns (requirement - (data path - clock path skew + uncertainty)) Source: u_datarecovery_d5_i (FF) Destination: u_datarecovery_d4_i (FF) Requirement: 2.400ns Data Path Delay: 0.801ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: clk_180 rising at 1.600ns Destination Clock: clk_90 rising at 4.000ns Clock Uncertainty: 0.200ns
why the requirement is different between these two data path? I need them both works at the same frequency.
Thanks.