Hi,
I have the following problem:
The Altera Cyclone device I am using does have two PLLs.
Because of the fact that I am using only one PLL the compiler seems to use PLL1 on bank 1 of the device.
But I need to route the external clock output of the PLL to bank 3 of the device. For that purpose I need PLL2 at bank 3 to be used.
How can I tell the compiler not to use PLL1 (bank 1) but PLL2 (bank 3) ? Is there some option?
I would be very thankful for your help.
Besr regards André V.