Hi
I've got a question concerning the use of BRAM connected to the Dat
Cache Unit. Does the processor still use the internal D-Cache Arra when BRAM is used? If that were the case, is there any possibility t disable the D-Cache Array, so that the processor is forced to use th connected BRAM
Thx in advance
Pi
The PPC caches are built into the processor core. They can be enabled or disabled for any 128MB memory region in real mode (MMU not used) or for any page size in virtual mode (MMU is used). Unless you are running an OS you will most likely run in real mode.
I assume that you hook the BRAM to the DSOCM port of the PPC. The DSOCM is not cacheable, never. This is even true if the DSOCM is mapped into a cacheable region. DSOCM has similar access characteristics as cache and thus does not need to be cached.
You might want to look at the OCM section in the PowerPC processor block reference guide to learn more about OCM. See
- Peter
Pit wrote:
The reason why I'm asking is the following I'm trying to design a hardware agent which ensures cache-coherenc between multiple processors, using an invalidation or an updat protocol. Therefor I planned to use OCM as Data Cache, as shown o page 26 (Figure 1-2) in the PPC405 Block Reference Guide. Th hardware agent would then be located somewhere between the processo (D-Cache Controller) and the On-Chip Memory. So the actual questio is: how does the processor use the OCM connected to the data cach controller? Does this approach make sense at all? : What I want to achieve is, that the processor somehow "bypasses" th D-Cache Array inside the Data Cache Unit and uses only OCM, so tha the hardware agent can react on data-writes to the cache (invalidat or update the corresponding cacheline in the other processors caches) Do you think, this is possible
Thanks so far
Pi
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