Xilinx EDK inferred dual port BRAM unconnected clkb

As part of an edk peripheral i have inferred 2 dual port BRAMs which synthesise and simulate correctly

For both BRAMs port a is controlled by the microblaze port b is controlled by fsm

BRAM 1 is used for PLB to peripheral communication in this case the input to port b data_in is never used or assigned

BRAM 2 is used for peripheral to PLB communication in this case the input to port b *data_out* is never used or assigned

when i import the peripheral into edk during MAP it gives me the following error

ERROR:LIT:459 - DATA_WIDTH_B is set to 36 for RAMB16BWER symbol "physical_group_plb_pipeline_simulator_0/plb_pipeline_simulator_0/ USER_LOGIC_ I/read_wrapper_dout/plb_pipeline_simulator_0/ plb_pipeline_simulator_0/USE R_LOGIC_I/Inst_pipeline_simulator/Mram_IP2Pipe_BRAM". This requires CLKB, REGCEB, ENB, RSTB and WEB[0-3] to be connected. Errors found during logical drc.

Following this error back i noticed when xst is inferring one of the BRAMS it doesn't connect clkb

----------------------------------------------------------------------- | ram_type | Block

----------------------------------------------------------------------- | Port A | aspect ratio | 512-word x 20-bit | mode | write-first | clkA | connected to signal | enA | connected to signal | weA | connected to signal | addrA | connected to signal | diA | connected to signal | doA | connected to signal

----------------------------------------------------------------------- | optimisation | speed

----------------------------------------------------------------------- | Port B | aspect ratio | 512-word x 20-bit | mode | write-first | weB | connected to signal | addrB | connected to signal | diB | connected to signal

----------------------------------------------------------------------- | optimisation | speed

-----------------------------------------------------------------------

So my question

Why does xst not connect clkb to the port b of the second BRAM?

I
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