Hallo, I would insert multichannel opb sdram controller into a project.
I would use xcl bus to access read/write datas into a integer matrix.
I would know if every time I would perform read/write operations into a element of the matrix I need to:1) disable data cache 2) init cache with address of matrix element 3) enable cache
Is it correct?
Following that the system copy the region of sdram into bram cache to perform operations on it?
Many Thanks Marco