Daniel,
Variables provide locality of reference (signals are NOT declarable at the process level). Variable assignments and references work just like they read, unlike signals. Variable assignments allow complex expressions to be simplified instead of repeated. Variables work. Period.
The synthesis tool creates a circuit that behaves, on a clock cycle basis, in the same manner as the RTL description behaves, whether you use signals or variables. I prefer a style that makes the behavioral aspect more clear, perhaps even at the expense of the structural aspect. In 17+ years of vhdl use, I've had far more bugs that were caused by behavioral problems than structural ones.
Besides, when you turn on pipelining and retiming optimizations, all your carefully constructed distribution of gates between registers goes right out the window. And then you don't even have a good behavioral description to fall back on.
I heard the similar arguments for separate combinatorial and clocked processes for years too: you need to be able to see the gates and registers. Why use an HDL to write a netlist?
That said, there are times when the structure is critical to the function (synchronization boundaries, for example). These are the times when I fall back on more explicit structural coding styles, if for no other reason than to better support code reviews.
Andy