The definition of comnatorial prcess?

The following topic may be one of the longest debate in vhdl group:

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The debute focus later turns to which is best way to use one sequential process or two combinarotial process and sequential process.

The most important and strange thing is that I cannot even find the word "combinarotial" in VHDL-2002 specification.

I want to grammarly define a combinatorial process which cannot have a clock statement in one of my thinking.

process_statement_part ::= { sequential_statement }

sequential_statement ::= wait_statement | assertion_statement | report_statement | signal_assignment_statement | variable_assignment_statement | procedure_call_statement | if_statement | case_statement | loop_statement | next_statement | exit_statement | return_statement | null_statement

combinatorial_process_statement_part ::= { combinatorial_sequential_statement }

combinatorial_sequential_statement ::= assertion_statement -- wait_statement is deleted here !!! | report_statement | signal_assignment_statement | variable_assignment_statement | procedure_call_statement | if_statement | case_statement | loop_statement | next_statement | exit_statement | return_statement | null_statement

Weng

Reply to
Weng Tianxiang
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I know verilog much better than VHDL, but ...

It might not be related to a VHDL specification.

Well, yes, but you probably also shouldn't have any type of latch, such as you might build out of NAND gates. But some kinds of feedback loops might be allowed. (An always interesting question is the end-around carry in ones-complement adders.)

I will guess, then, that in some cases it isn't possible to prove that a given logic block is, or isn't, combinatorial.

-- glen

Reply to
glen herrmannsfeldt

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The definition I always use for combinational logic is

"The steady-state value of a combinational logic function is purely defined by boolean logic functions of the steady state value of the inputs."

This implies no memory (state).

VHDL, as a modelling language, allows you to describe such behaviour, but it isn't defined in the language.

A different approach has been taken in SystemVerilog, where keywords always_comb, always_latch, and always_ff have been introduced to allow the designer to describe design intent in the simulation model.

VHDL just does whatever you tell it to, it's up to you to tell it to do "the right thing" with regard to the hardware you want to model.

regards Alan

--
Alan Fitch
Reply to
Alan Fitch

(snip, I wrote)

(snip)

Sounds good to me. As far as I know, though, there isn't any simple test for it.

Also, no guarantee on how fast the output gets to where it is suppose to be.

So far I haven't been interested in SystemVerilog.

-- glen

Reply to
glen herrmannsfeldt

Am Donnerstag, 28. Juni 2012 20:14:33 UTC+2 schrieb Weng Tianxiang:

Hi Weng, I think the discussion you mentioned above is caused by a big misunderstand= ing of what the word "sequential" is refering to.

"sequential" with respect to the VHDL language means, that the statements i= nside a block are evaluated one after another. This has no connection whats= oever to the resulting circuit.

The opposite of "sequential" here is "concurrent", not "combinatorical". "Combinatorical" has no meaning for the language, and therefore doesn't nee= d to be specified anywhere in the standard. But when you look into part 4(?= ) of the Standard (The synthesis part) there you find the term "synchronous= description". Such a "synchronous description" results in some circuit wit= h registers. everything else is just gates, and with feedbacks or incomplet= e conditional branches sometimes to latches, which are identified by the to= ols, so the designer can decide wether they are intended or not.

Therfore there is no need to make up fancy words and lenghty descriptions f= or things that are nicely covered in one compact and generic description.

The contradiction of such a request can already be found in the proposed sy= ntax description: combinatorial_process_statement_part ::=3D { combinatorial_SEQUENTIAL_statement }

Does this ease up something? and how to avoid the usage of=20 =20 if rising_edge(clk) then

in such a dedicated combinatorical process.

and what if in a dedicated non_combinatorical process only this is used: =20 wait for 1 ns;

but no event related stuff?=20

So there's no gain, just increased confusion and waste of paper.

A process does what the designer wants it to do. Either synchronous or combinatorical. For that purpose one grammar specific= ation is sufficient.

Apply Occams razor.

Have a nice synthesis Eilert

Reply to
goouse99

nding of what the word "sequential" is refering to.

inside a block are evaluated one after another. This has no connection wha= tsoever to the resulting circuit.

eed to be specified anywhere in the standard. But when you look into part 4= (?) of the Standard (The synthesis part) there you find the term "synchrono= us description". Such a "synchronous description" results in some circuit w= ith registers. everything else is just gates, and with feedbacks or incompl= ete conditional branches sometimes to latches, which are identified by the = tools, so the designer can decide wether they are intended or not.

for things that are nicely covered in one compact and generic description.

syntax description:

ication is sufficient.

Eilert, Actually I want to create something new in HDL, a new type of process, that= leads to the problem: the concept of a concurrent combinatorial process:= =20

  1. The new process is a concurrent process as other processes are.
  2. In the new process, no traditional clock statement, explicit or implicit= , is allowed.
  3. In the new process all sequential statements, excluding wait statement, = are allowed.

Someone may ask that what "a traditional clock statement" means? All those = who write logic programming in VHDL know it, but there is never a definitio= n of it in VHDL language. I would like to have someone to fill the gap.

Is it clear enough now?

  1. " if rising_edge(clk) then": the situation will be excluded by note 2, n= ot by grammar.

  1. "wait for 1 ns;": wait statement is prohibited in the grammar.

I don't see any conflicts now.

I appreciate the SystemVerilog grammar by declaring three types of processe= s explicitly: a. always_comb;=20 b. always_latch; c. always_ff.

No any ambiguity is generated in any situations.

Thank you for your discussion.=20

Weng

Reply to
Weng Tianxiang

..

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tanding of what the word "sequential" is refering to.

ts inside a block are evaluated one after another. This has no connection w= hatsoever to the resulting circuit.

.

need to be specified anywhere in the standard. But when you look into part= 4(?) of the Standard (The synthesis part) there you find the term "synchro= nous description". Such a "synchronous description" results in some circuit= with registers. everything else is just gates, and with feedbacks or incom= plete conditional branches sometimes to latches, which are identified by th= e tools, so the designer can decide wether they are intended or not.

ns for things that are nicely covered in one compact and generic descriptio= n.

d syntax description:

:

ification is sufficient.

at leads to the problem: the concept of a concurrent combinatorial process:

it, is allowed.

, are allowed.

e who write logic programming in VHDL know it, but there is never a definit= ion of it in VHDL language. I would like to have someone to fill the gap.

not by grammar.

ses explicitly:

I don't see the need for such a new construct. If you want a combinatorial circuit then write the process with all the inputs in the sensitivity list, use no feedback of any kind and make sure the outputs are defined for all combinations of inputs. If you want a sequential circuit add the reset (if used) and the clock to the sensitivity list, use all the feedback you want or don't want and don't worry about which combinations of inputs you specify or not.

Your "new process" type defined above is not guaranteed to generate combinatorial logic because you don't exclude feedback or require all input combinations to be defined. Many a new HDL designer has inadvertently left out some input combinations or used feedback and ended up with latches. Heck, even experienced designers do this once in a while.

The resulting logic comes from how you describe the process, not what label you attach.

Rick

Reply to
rickman

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ents inside a block are evaluated one after another. This has no connection= whatsoever to the resulting circuit.

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't need to be specified anywhere in the standard. But when you look into pa= rt 4(?) of the Standard (The synthesis part) there you find the term "synch= ronous description". Such a "synchronous description" results in some circu= it with registers. everything else is just gates, and with feedbacks or inc= omplete conditional branches sometimes to latches, which are identified by = the tools, so the designer can decide wether they are intended or not.

ions for things that are nicely covered in one compact and generic descript= ion.

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ose who write logic programming in VHDL know it, but there is never a defin= ition of it in VHDL language. I would like to have someone to fill the gap.

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esses explicitly:

Rick, Your following comment hit the point: " Your "new process" type defined above is not guaranteed to generate=20 combinatorial logic because you don't exclude feedback or require all=20 input combinations to be defined."

If there is no clock statement and not wait statement allowed in a process,= how do you generate a ff? latch is allowed to be generated in my case.

Weng

Reply to
Weng Tianxiang

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ements inside a block are evaluated one after another. This has no connecti= on whatsoever to the resulting circuit.

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sn't need to be specified anywhere in the standard. But when you look into = part 4(?) of the Standard (The synthesis part) there you find the term "syn= chronous description". Such a "synchronous description" results in some cir= cuit with registers. everything else is just gates, and with feedbacks or i= ncomplete conditional branches sometimes to latches, which are identified b= y the tools, so the designer can decide wether they are intended or not.

ptions for things that are nicely covered in one compact and generic descri= ption.

posed syntax description:

used:

specification is sufficient.

, that leads to the problem: the concept of a concurrent combinatorial proc= ess:

plicit, is allowed.

ment, are allowed.

those who write logic programming in VHDL know it, but there is never a def= inition of it in VHDL language. I would like to have someone to fill the ga= p.

e 2, not by grammar.

ocesses explicitly:

s, how do you generate a ff? latch is allowed to be generated in my case.

A latch is a sequential device. It has memory and that is how "sequential" is defined.

As I said, I don't see the value of your proposition. What are you trying to accomplish?

Rick

Reply to
rickman

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have a

understanding of what the word "sequential" is refering to.

atements inside a block are evaluated one after another. This has no connec= tion whatsoever to the resulting circuit.

rical".

oesn't need to be specified anywhere in the standard. But when you look int= o part 4(?) of the Standard (The synthesis part) there you find the term "s= ynchronous description". Such a "synchronous description" results in some c= ircuit with registers. everything else is just gates, and with feedbacks or= incomplete conditional branches sometimes to latches, which are identified= by the tools, so the designer can decide wether they are intended or not.

riptions for things that are nicely covered in one compact and generic desc= ription.

roposed syntax description:

s used:

r specification is sufficient.

ss, that leads to the problem: the concept of a concurrent combinatorial pr= ocess:

implicit, is allowed.

tement, are allowed.

l those who write logic programming in VHDL know it, but there is never a d= efinition of it in VHDL language. I would like to have someone to fill the = gap.

ote 2, not by grammar.

processes explicitly:

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ess, how do you generate a ff? latch is allowed to be generated in my case.

Hi Rick, I hope to publish my paper as soon as possible, but I cannot disclose its d= etails now.

I would like to ask you the question you mentioned earlier and hope you giv= e me an exception: If there is no clock statement and not wait statement allowed in a process,= how do you generate a ff?=20

latch is allowed to be generated in my case.

After my paper publication, you may have another real opportunity to commen= t on IF it is useful.

Weng

Reply to
Weng Tianxiang

p:

/bd...

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ave a

derstanding of what the word "sequential" is refering to.

ements inside a block are evaluated one after another. This has no connecti= on whatsoever to the resulting circuit.

cal".

sn't need to be specified anywhere in the standard. But when you look into = part 4(?) of the Standard (The synthesis part) there you find the term "syn= chronous description". Such a "synchronous description" results in some cir= cuit with registers. everything else is just gates, and with feedbacks or i= ncomplete conditional branches sometimes to latches, which are identified b= y the tools, so the designer can decide wether they are intended or not.

ptions for things that are nicely covered in one compact and generic descri= ption.

posed syntax description:

used:

specification is sufficient.

, that leads to the problem: the concept of a concurrent combinatorial proc= ess:

plicit, is allowed.

ment, are allowed.

those who write logic programming in VHDL know it, but there is never a def= inition of it in VHDL language. I would like to have someone to fill the ga= p.

e 2, not by grammar.

ocesses explicitly:

s, how do you generate a ff? latch is allowed to be generated in my case.

You've forgotten a very basic principle...EVERY logic circuit (including fl= ip flops) can be described with nothing more than nand (or nor) gates. A f= lip flop can be described with nand gates. The (likely) fact that no synth= esis tool on the market will take a nand gate description and synthesize a = flip flop simply reflects the limitations of the tools at this point in tim= e. There are many such limitations, but those are all examples where synth= esis tools are not able to adhere to the language defintion while also synt= hesizing the optimal circuit. Limitations can disappear in the future.

In any case, since a flip flop can be described with only nand or nor gates= , then it is not possible to limit the current scope of the language to pre= vent a flip flop from being described in HDL. Therefore, any such definiti= on that you come up with to try to prevent a flip flop from being described= will ultimately have a hole in the definition.

Kevin Jennings

Reply to
KJ

g:

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have a

understanding of what the word "sequential" is refering to.

atements inside a block are evaluated one after another. This has no connec= tion whatsoever to the resulting circuit.

rical".

oesn't need to be specified anywhere in the standard. But when you look int= o part 4(?) of the Standard (The synthesis part) there you find the term "s= ynchronous description". Such a "synchronous description" results in some c= ircuit with registers. everything else is just gates, and with feedbacks or= incomplete conditional branches sometimes to latches, which are identified= by the tools, so the designer can decide wether they are intended or not.

riptions for things that are nicely covered in one compact and generic desc= ription.

roposed syntax description:

s used:

r specification is sufficient.

ss, that leads to the problem: the concept of a concurrent combinatorial pr= ocess:

implicit, is allowed.

tement, are allowed.

l those who write logic programming in VHDL know it, but there is never a d= efinition of it in VHDL language. I would like to have someone to fill the = gap.

ote 2, not by grammar.

processes explicitly:

=20

=20

ess, how do you generate a ff? latch is allowed to be generated in my case.

flip flops) can be described with nothing more than nand (or nor) gates. A= flip flop can be described with nand gates. The (likely) fact that no syn= thesis tool on the market will take a nand gate description and synthesize = a flip flop simply reflects the limitations of the tools at this point in t= ime. There are many such limitations, but those are all examples where syn= thesis tools are not able to adhere to the language defintion while also sy= nthesizing the optimal circuit. Limitations can disappear in the future.

es, then it is not possible to limit the current scope of the language to p= revent a flip flop from being described in HDL. Therefore, any such defini= tion that you come up with to try to prevent a flip flop from being describ= ed will ultimately have a hole in the definition.

KJ, You are right, but I think you are nitpicking. "A flip flop can be described with nand gates. The (likely) fact that no s= ynthesis tool on the market will take a nand gate description and synthesiz= e a flip flop simply reflects the limitations of the tools at this point in= time."

James comment on VHDL-2008 in comp.lang.vhdl group is very useful and I thi= nk his comment has already given the right answer I am looking for.

Thank you.

Weng

Reply to
Weng Tianxiang

ang:

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statements inside a block are evaluated one after another. This has no conn= ection whatsoever to the resulting circuit.

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doesn't need to be specified anywhere in the standard. But when you look i= nto part 4(?) of the Standard (The synthesis part) there you find the term = "synchronous description". Such a "synchronous description" results in some= circuit with registers. everything else is just gates, and with feedbacks = or incomplete conditional branches sometimes to latches, which are identifi= ed by the tools, so the designer can decide wether they are intended or not= .

scriptions for things that are nicely covered in one compact and generic de= scription.

proposed syntax description:

is used:

.

mar specification is sufficient.

cess, that leads to the problem: the concept of a concurrent combinatorial = process:

.

r implicit, is allowed.

tatement, are allowed.

All those who write logic programming in VHDL know it, but there is never a= definition of it in VHDL language. I would like to have someone to fill th= e gap.

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details now.

ive me an exception:

s, how do you generate a ff?

ent on IF it is useful.

I'm sorry, but I don't understand your question. A latch is a type of flipflop. I don't know what you mean when you say it is "allowed" to be generated. I also don't know what you mean by "clock statement".

All of the code I have seen describes the behavior of a ff, either edge sensitive or level sensitive. There are no "clock statements" that I know of. You wait for an edge and make an assignment and do nothing the rest of the time, or you wait for a level and make an assignment and do nothing the rest of the time. What makes it "sequential" is the "do nothing" the rest of the time when the sequential logic "remembers" the previously calculated state. Combinatorial logic is always a direct reflection of all inputs, all the time. There is no "remember".

If you are suggesting some sort of formalism that treats latches as combinatorial logic then by my reckoning you are in left field.

Rick

Reply to
rickman

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mment on IF it is useful.

Hi Rick, Thank you for your concern.

I actually find that James has given the right answer: It requires the form= at he suggested: process(all) that says what I want to say.

I have abandoned the idea to use the clock statement or other inaccurate de= scriptions.

Weng

Reply to
Weng Tianxiang

ang:

group:

read/bd...

l

nd the

ot have a

isunderstanding of what the word "sequential" is refering to.

statements inside a block are evaluated one after another. This has no conn= ection whatsoever to the resulting circuit.

torical".

doesn't need to be specified anywhere in the standard. But when you look i= nto part 4(?) of the Standard (The synthesis part) there you find the term = "synchronous description". Such a "synchronous description" results in some= circuit with registers. everything else is just gates, and with feedbacks = or incomplete conditional branches sometimes to latches, which are identifi= ed by the tools, so the designer can decide wether they are intended or not= .

scriptions for things that are nicely covered in one compact and generic de= scription.

proposed syntax description:

is used:

.

mar specification is sufficient.

cess, that leads to the problem: the concept of a concurrent combinatorial = process:

.

r implicit, is allowed.

tatement, are allowed.

All those who write logic programming in VHDL know it, but there is never a= definition of it in VHDL language. I would like to have someone to fill th= e gap.

note 2, not by grammar.

f processes explicitly:

a

ll

once

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ocess, how do you generate a ff? latch is allowed to be generated in my cas= e.

g flip flops) can be described with nothing more than nand (or nor) gates. = =A0A flip flop can be described with nand gates. =A0The (likely) fact that = no synthesis tool on the market will take a nand gate description and synth= esize a flip flop simply reflects the limitations of the tools at this poin= t in time. =A0There are many such limitations, but those are all examples w= here synthesis tools are not able to adhere to the language defintion while= also synthesizing the optimal circuit. =A0Limitations can disappear in the= future.

ates, then it is not possible to limit the current scope of the language to= prevent a flip flop from being described in HDL. =A0Therefore, any such de= finition that you come up with to try to prevent a flip flop from being des= cribed will ultimately have a hole in the definition.

no synthesis tool on the market will take a nand gate description and synth= esize a flip flop simply reflects the limitations of the tools at this poin= t in time."

hink his comment has already given the right answer I am looking for.

I think you have a different perspective on what synthesis tools do compared to my experience. The tools don't know anything about what you are trying to do or whether you are describing NAND gates or FFs. All they know is the description you give and they figure out how to implement it. If you use a bunch of ands and ors to describe how a FF works I would not doubt for a moment that the tools would utilize a FF. But the only way to tell is to try it.

The real issue is that your idea of trying to "force" the tool to use combinatorial logic or FFs or latches is not going to work. What happens when you try to use combinatorial logic and you fail to fully define the behavior? Will it not generate a latch? What will it generate?

Rick

Reply to
rickman

(snip)

I agree.

Normally you can't make a traditional edge tricgered FF out of orginary gates. You can make a transparent latch, and some other devices with state.

-- glen

Reply to
glen herrmannsfeldt

Why do you say that? With two transparent latches (a master and a slave) you can make an edge triggered flip-flop, right?

Even wikipedia has a some examples.

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I hacked a D flip-flop in a 16L8 once... as a fix. I don't recall being too grossed out by it.

-- Rob.

Reply to
Rob Doyle

(snip, I wrote)

As it was explained to me many years ago, you want a different threshold for the two. Maybe that isn't always necessary, but only an optimization, or maybe technology dependent.

I will have to look at those.

-- glen

Reply to
glen herrmannsfeldt

Hi Rick, when I'm teaching synthesis as part of teaching VHDL or Verilog, I tend to use "transparent latch" for level sensitive latches, and "edge-triggered D-type flip-flop" for D-type flip-flops. I then abbreviate these to "latch" and "flip-flop". So by my usage, I don't regard a (transparent) latch as a flip-flop. However when I worked at Philips Semiconductors years ago, people used "latch" to describe D-types and transparent latches!

So I don't know if "latch" = "transparent latch" or "edge triggered flip-flop": hence using "transparent" and "edge-triggered" when teaching to avoid confusion.

he suggested: process(all) that says what I want to say.

descriptions.

Hi Weng, if you follow the definition of combinational logic I gave before (the steady state value of the output is *only* a unique function of the steady state values of the inputs) then you must follow three rules

  1. complete sensitivity list (like VHDL 2008 (all) as Jim said)
  2. no feedback
  3. no incomplete assignment of outputs

Some examples

process(all) begin o

Reply to
Alan Fitch

format he suggested: process(all) that says what I want to say.

descriptions.

Alan, Rick, glen, Rob, Thanks for your joining my discussions.

I think I have already got the right answer from James, by using process(all).

Alan, your suggestion of the following text may be right for a fully combinatorial logic.

  1. complete sensitivity list (like VHDL 2008 (all) as Jim said)
  2. no feedback
  3. no incomplete assignment of outputs

But I don't have to limit it grammatically in my case. If someone uses feedback in my proposed something, it would be an error which the designer is responsible to correct it that would lead him to delete the feedback.

Thank all of you.

Weng

Reply to
Weng Tianxiang

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