Xilinx EDK PLB/OPB bridge (and IPIF)

Hi, I'm facing a stange behaviour of the PLB-IPIF interface and I would like an advice about it. I've designed my own plb bus master wich loads data from a sram connected to an opb-emc unit. The plb and opb bus are connected through a bridge. The plb bus is 64 bit (double word) and the opb and sram are 32 bits (word). I need to perform variable burst length (because it depends on my data) and I have a very strange problem. When the burst length is 9, it seems that the burst is transformed to two 16 word sram accesses. This behaviour is correct (described in documents) but when I perform a second 9 double word burst, the two are messed !! Indeed, the IPIF signals a complete transfert when the 9 double words are loaded but the second 16 word sram access is still in progress. The second 9 double word burst is messed with the previous unfinished sram accesses !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! There are no error signals and so on.... Is it a bug or did I missed something ? Is this corrected in new versions ? (I'm using ISE-62i and edk 6.2)

What sould I do ?

Thanks a lot


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Mancini Stephane
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