synplify pro generates negative slack

Wrong.

An SRL16 *functions* just like a simple shift register, but physically it is a special configuration of a LUT primitive. The setup time and clock-to-out time is very different from a FF primitive in the fabric. When you are doing a high-speed design, you should always try to make the last stage of your shift register pipeline use a dedicated FF. Most synthesis tools will do this for your automatically if you just write a straightforward shift register in RTL. No need to go instantiating things.

-Ben-

So what your are implying is that its advisable to write the code in the following way

--------------------------------------------------------------------------------------------------------------------------------------------- PROCESS(clock,reset) begin if reset = '1' then en4

If I were having trouble making timing, I would use a generic shifter. It is faster in nS and in work hours. Registers are free on many fpga designs.

-- Mike Treseler

I have recently started(1 week) using Synplify pro. For two years in my fpga designs I never used synplify pro. For most of the generic component I used to use core generator and then instantiate those component in my vhdl code. I was using xilinx XST extensivley and hence never go these problems. Unfortunately before using synplify pro for mycurrent design I have used core genrator in most of the components. So now I am thingkin of cleaning up the code by changing the cores for example adders , subtractors, SRL16s, BRAMs, ROMS etc to vhdl statements. Are ther any good documents for vhdl coding styles to infer the various components in synplify pro?

Thanks for all the suggestions above.

Next time post to comp.lang.vhdl.

Start with the Synplify pro vhdl synthesis guide. Most of the core generator blocks can be replaced by a few lines of vhdl code, but there is a learning period.

Here's some brand A examples :

Here's some brand X examples :

Here are my examples.

Good luck.

-- Mike Treseler