I am having problems gtting the retiming feature in Synplify to work. I am coding in a style that utilizes the behavioural retiming(BRT) of synopsys. I code a mac as simple ((a*b) + c) + bulk delay. Synopsys then retimes the code by pipelining the mac.
When I try to test this code in an fpga, Synplify does not retime the registers properly. Has anyone else tried this?
thanks John