hi , can anyone please explain how the setup/hold time for a flip flop can be negative????
also what is maximum frequency of operation of a circuit detemined wholly by the setup time equation , or are there other factors too?
negative hold/setup time ???
Feb 27, 2005
1 Replies
The setup time is before the clock edge. The hold time is usually the time that the 'D' input must be held after the clock edge. However, on some logic families, the 'D' input can be released before the clock edge due to the internal delay of the flip flop. This would be considered a negative value.
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