Folks,
[Beginner] I've been trying to decypher a reference design that contains verilog source and instantiation of modules CLKDLL, IBUFG, and BUFG. Reading through the source, seven_seg.v, I find the instantiation of objects CLKDLL, IBUFG, and BUFG, but no source verilog for them. It was provided with development board Xilinx Spartan-3 LC Kit from Avnet*. I am using ISE 6.3.03i from Xilinx to load the design onto the board. The problem I am having is that there is no source provided for these modules, so I am not sure if the ISE fills in their definition given that project targets the xc3s400-4pq208, or if the user constraint file (UCF) provides the necessary details, given that the FPGA chip itself provides the hardware (digital clock manager, i.e. DCM) that implements the reference.** Since the reference design works, how are these modules being resolved by the synthesizer (xst) or in the design flow (e.g. mapper, etc)? If they are coming from a library, how can I find the documentation explaining these modules? What other verilog modules are available for us in designs (e.g. where is this documented)? I know, for example, that this chip has a multiplier.Thanks for reading, BEA
*module seven_seg (CLK, PUSH, DIP, DISPLAY, LED);
// Input Declarations input CLK; //surface-mount 50MHz oscillator input [2:1] PUSH; //push-button switches input [3:0] DIP; //DIP[3] is SW3[1] on the board
// Output Declarations output [6:0] DISPLAY; //7-segment display DD1 output [4:1] LED; //user LEDs
// Input Registers reg [3:0] DIP_r [3:0]; // 4x4 array to hold registered versions of DIP reg [3:0] DIP_d; // debounced DIP reg [3:0] PUSH1_r; // registered version of PUSH1 reg [3:0] PUSH2_r; // registered version of PUSH2 reg PUSH1_d; // debounced PUSH1 reg PUSH2_d; // debounced PUSH2
// Output Registers reg [4:1] LED; reg [6:0] DISPLAY;
// Other Registers reg [22:0] led_count; reg [3:0] led_seg_count; reg reset; // high-asserted reset
// Internal signals wire led_count_en; wire clk_i, clk_fb, clk0, clkdv, clk_div16; integer i;
/* Using CLKDLL to divide the input 50 MHz clock by 16 resulting in a 3.125 MHz internal clock */ IBUFG U1 ( .I(CLK), .O(clk_i));
CLKDLL dll_div_by_16 ( .CLKIN(clk_i), .CLKFB(clk_fb), .RST(1'b0), .CLK0(clk0), .CLK90(), .CLK180(), .CLK270(), .CLK2X(), .CLKDV(clkdv), .LOCKED());
BUFG U3 ( .I(clk0), .O(clk_fb)); BUFG U4 ( .I(clkdv), .O(clk_div16));
// Register and debounce push buttons and switches // If the bouncy signal is high, 4 consecutive lows required to pull it low // If the bouncy signal is low, 4 consecutive highs required to pull it high always @(posedge clk_div16) begin PUSH1_r[0]