Hi, I'm using Xilinx 8.2.03i and I get an Error Xst:528 "Multi-source in Unit ..." It's a wire in a submodule and i checked the code: The signal is an output to module A and an input to module B. There is no other assignment to this signal. Inside module B the signal is only on the right-side of any "=" assignments.
Could there be a bug in Xst when using a design containig both VHDL and verilog files?
Timo
We use EDK, ISE, and ModelSim with mixed VHDL and Verilog designs, and it works. We have instances of VHDL instantiating Verilog modules, and Verilog instantiating VHDL. We are currently using 8.1 and 8.2.
The biggest problem that we have encountered is when passing generics from VHDL to Verilog. For example, if we are passing a generic from VHDL to Verilog, and Verilog considers it an integer, ISE wants it done one way, and ModelSim wants it done a different way.
The rest of the error message should tell you what it thinks the multiple sources are, track that down to see if they really exit.
Regards,
John McCaskill
Are module A and B in this instance different languages? If so make sure that the port connections are all properly matched. I've seen cases where the error message doesn't necessarily give useful information when you cross language boundaries, so it may not really be a multi-source issue.
Also make sure that the sourcing module doesn't report a multi- source if you build it alone. If you use Verilog, XST will complain of multi-source if you assign a register in more than one always block.
Regards, Gabor
If you have Modelsim, this could be another use for the "drivers" command.
- Brian
Problem solved! Thanks for your answers. I dont know exactly what it was, but i must have been something with `define and `ifdef statements in the verilog code...
Timo Gerber schrieb:
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