synthesis error

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map(clk=>clk,reset=>reset,ad=>ad,we_n=>we_n,oe_n=>oe_n,dio_a=>dio_a,ce_a_n=>ce_a_n,

ub_a_n=>ub_a_n,lb_a_n=>lb_a_n,dio_b=>dio_b,ce_b_n=>ce_b_n,ub_b_n=>ub_b_n,lb_b_n=>lb_b_n,

mem=>mem,rw=>mem_rw,addr=>mem_addr,data_f2s=>mem_data_f2s,data_s2f=>mem_data_s2f,ready=>mem_ready);

h2s_ascii is neither an input nor is it assigned anything .. it is a floating undefined net .. that is your problem.

Mike

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It assigned to something, but we and the synthesizer don't know what it is as the hex2ascii component wasn't defined. There was probably another synthesis warning on the "hex2a : entity hex2ascii" line.

Ed McGettigan

-- Xilinx Inc.

You connect h2a_ascii with tx_data. I guess tx_data is the real problem, as it is connected to gnd in process and h2a_ascii in concurrent statement. Without the component declarations I can only guess, that the entity inside drives h2a and sources tx_data. It would be a good idea to include the component declarations. I know why I use std_ulogic instead of std_logic :).

bye Thomas

What happened in simulation?

In Modelsim, you can use the "drivers" command to find out exactly what drivers are connected to the signal in question; that gos a long way to finding the problem.

- Brian