synthesis error

Hi, synthesizing the following code yields an error.

CODE :

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 16:22:54 06/23/2008

-- Design Name:

-- Module Name: main - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity main is port( clk,reset : in std_logic; btn: std_logic_vector(2 downto 0); rx : in std_logic; tx : out std_logic; led: out std_logic_vector(7 downto 0); sseg : out std_logic_vector(7 downto 0); an : out std_logic_vector(3 downto 0);

-- to/from chip ad : out std_logic_vector(17 downto 0); we_n, oe_n : out std_logic; -- SRAM chip a dio_a : inout std_logic_vector(15 downto 0); ce_a_n,ub_a_n,lb_a_n : out std_logic; -- SRAM chip b dio_b : inout std_logic_vector(15 downto 0); ce_b_n,ub_b_n,lb_b_n : out std_logic ); end main;

architecture Behavioral of main is signal tx_full, rx_empty: std_logic; signal rx_data,tx_data : std_logic_vector(7 downto 0); signal btn_tick: std_logic; signal mem : std_logic; signal mem_rw : std_logic; signal mem_addr : std_logic_vector(17 downto 0); signal mem_data_f2s : std_logic_vector(31 downto 0); signal mem_data_s2f : std_logic_vector(31 downto 0); signal mem_ready : std_logic; signal h2a_hex : std_logic_vector(3 downto 0); signal h2a_ascii : std_logic_vector(7 downto 0); signal wr_uart,rd_uart : std_logic; type state_t is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10); type regs_t is record state : state_t; led : std_logic_vector(7 downto 0); hex : unsigned(3 downto 0); end record; signal r_reg,r_next : regs_t; begin uart_unit : entity uart port map(clk=>clk,reset=>reset,rd_uart=>rd_uart,wr_uart=>wr_uart, rx=>rx,w_data=>tx_data,tx_full=>tx_full,rx_empty=>rx_empty, r_data=>rx_data,tx=>tx); btn_db_unit : entity debounce port map(clk=>clk,reset=>reset,button=>btn(0),db_level=>open,db_tick=>btn_tick); sram_unit : entity sram_ctrl port map(clk=>clk,reset=>reset,ad=>ad,we_n=>we_n,oe_n=>oe_n,dio_a=>dio_a,ce_a_n=>ce_a_n, ub_a_n=>ub_a_n,lb_a_n=>lb_a_n,dio_b=>dio_b,ce_b_n=>ce_b_n,ub_b_n=>ub_b_n,lb_b_n=>lb_b_n, mem=>mem,rw=>mem_rw,addr=>mem_addr,data_f2s=>mem_data_f2s,data_s2f=>mem_data_s2f,ready=>mem_ready); hex2a : entity hex2ascii port map(hex=>h2a_hex,ascii=>h2a_ascii); an