Confused with "task" keyword.

I wrote a task to feed test vectors to my design, however, I realized some differences between "task" and the normal state machines I used to do. One sample code below, I am expecting the the signal "trd_sample" to be delayed by one cycle of "trc", i.e. 2nd posedge of trc. However, why does the simulation shows on the first posedge of trc?

I have put the modelsim waveform here.

formatting link

Thank you in advance.

module sim; reg clk; reg rst_n;

reg trw; reg [3:0] trd; reg trc;

reg [3:0] trd_sample;

always #5 clk

Reply to
Confused Frank
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Frank, I am confused as to what behavior you are expecting. Your always@ block at the end will make trd_sample equal to trd every time that there is a posedge of trc. Since you are using non-blocking assigments, the signals are assigned immediately, with no regards to clocks. That also means that there is also no 'guarantee' of the order of assignment either. When you have three non-blocking assignments in sequence, the simulator might not execute them in the same order as written, generating some interesting race conditions.


Reply to
Chuck Gales

Thank you Chuck. I am done by putting a unit delay at txd & trw, and I have better understanding over non/blocking assignment now.

Reply to
Confused Frank

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