I wrote a task to feed test vectors to my design, however, I realized some differences between "task" and the normal state machines I used to do. One sample code below, I am expecting the the signal "trd_sample" to be delayed by one cycle of "trc", i.e. 2nd posedge of trc. However, why does the simulation shows on the first posedge of trc?
I have put the modelsim waveform here.
Thank you in advance.
module sim; reg clk; reg rst_n;
reg trw; reg [3:0] trd; reg trc;
reg [3:0] trd_sample;
always #5 clk