I'm a total Verilog newbie, having just started yesterday but already finding it far less intimidating than the VHDL I thought I was going to have to deal with. I'm a systems software programmer with enough hardware knowledge to be dangerous, and a few projects under my belt (microcontroller based servo-style stuff). FWIW I'm not taking any classes on this stuff (yet?), just screwing around on my own.
I'm playing with the design of a multi-channel analog capture system, where I need an FPGA to take a number (4-16) of SPI inputs from stereo audio ADCs, and multiplex them all into a 16-bit bus with a single write strobe, to be connected to a Cypress EZ-USB FX2.
I'm pretty sure I've got almost all the logic in place, *except* for a clocking issue. The PCM audio SPI port includes an LRCLK (left-right clock) that goes high at the end of the left channel sample, then goes low at the end of the right channel sample.
The problem is that even with a lot of googling, I haven't been able to find (or recognize?) a way to create a pulse I can use to start the parallel output sequence, on *both* edges of the LRCLK:
SCLK .. _-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- .. DATA .. xxxxxxRRRRRRRRRRRRxxxxLLLLLLLLLLLLxxxxRRRRRRRRRRRRxx .. LRCLK .. __----------------________________----------------__ .. goal .. __-_______________-_______________-_______________-_ ..
Once I have the LRCLK edge pulse, I can start up the FSM that will drive each group of 16 bits to the output bus one at a time, based either on SCLK or another clock (safer with SCLK, as it stays a basic synchronous design AFAICT).
Any hints would be greatly appreciated, especially code fragments Also if anyone can suggest a good example-heavy, relatively theory-light book on Verilog FPGA design (e.g. "Verilog FPGA Design by Example for Dummies") that I might get...
TIA, Omega aka Erik Walthinsen email@example.com