ModelSim VHDL Pragmas

Generate statements?

-a

That's a solution to reducing the changes needed, but it doesn't fully automate the changes unless there's a way to detect which compiler is being used - Modelsim or synthesis. If you had a way to put your synthesis-specific code at the top of the file, you could use the - line option for vcom in Modelsim to start compilation after the synthesis only section, but I don't see this as very practical. If you were using Verilog I could think of a few ways to deal with this... In Verilog for example you can define a macro on the command line and then use `ifdef `else to exclude code that is for synthesis only.

Depending on the extent of your optional code, can you use two different architectures, & a configuration file to choose between them?

Thank you all for your responses. Unfortunately, I am sharing this code among people using different design flow and I don't want to change anybodies flow. For now, it seems the most reliable solution would be using generate statements, but I think we're going to just have to remember to hand comment out when it's time to synthesize.

Thanks again,

--Peter

You can use this old trick:

constant MODELSIM : boolean := false

-- synthesis translate_off or true

-- synthesis translate_on ;

then if MODELSIM then foo; else bar; end if;

or similar. Jonathan B will surely post a better solution in due course.

Thank you Tim,

You just made my day. I use Verilog, but work with EDK which has a strong VHDL bias. I have been having to work around problems with passing std_logic_vector generics to integer parameters and keeping multiple versions of EDK and ModelSim happy at the same time. This is a much more elegant solution than any of the others that I have come up with or had recomended to me.

Regards,

John McCaskill

You could use a generic and if statement inside a process or conditional assignment outside to select various parts of the code.

generic ( options: integer:=1); : :

concurrent_sig

you can exclude blocks of code from synthesis using the syn_translate on/off pragma, which will allow you to put sections of code that is only seen during simulation. This is useful for splitting out time multiplexed signals in a way that is easier to examine during simulation, for example. You can get a little creative with the syn_translate pragma to make a function that produces a signal that is active only in synthesis to block simulation of a chunk of logic too, although I haven't found much need for that.

Mine uses a function call, same idea though:

function synthesis_only return integer is variable temp: integer; begin temp:=1; --synthesis translate_off temp:=0; --synthesis translate_on return temp; end function synthesis_only;

if synthesis_only()=1 then...