Hi i'm currently working on a high-speed chip-to-chip serial interface FPGA interface, i would like to know some suggestions regarding FPGA differential signalling; especially the trace matching of pair of LVDS signal, and the whole Channel (set of LVDS signals; Tx_Frame, Tx_Clk, Tx_Data) etc. My application is for 622Mbps signalling rate. Anyone has an experience on this?
It's important to keep all signals' p-to-n length matched closely. This will insure that there is a clean cross between the p and n inputs of the input comparator during one-to-zero and zero-to-one transitions. You don't want a p input to change from zero to one while the n input is still stuck at a one.
For signal-to-signal length matching (in a source synchronous bus), you must consider the outputs' clock-to-out delay matching and the inputs' setup and hold time. There is no way to determine the length matching requirements without knowledge of the output and input characteristics.
I would recommend using a FPGA family that has internal 100ohm differential termination (within the input block). For Xilinx, this is V2Pro and above (watch the VCCO requirements carefully). This will make layout easier and give you the best setup and hold margin because at 622Mbps you're gonna need all you can get.
Hi Bob, I've matched the trace length withing 100mils is that OK? BTW, i use Spartan3 FPGA. Does having the DCI option in Spartan3 will eliminate the external termination resistor at the receiving end? One more thing, the other FPGA i'm using is Altera Cyclone-II FPGA(for this chip-to-chip connection)--and cyclone fpga needs at least 3 external resistors, my question is, can Spartan3's LVDS_DCI compensate for the external 'resistor network' at cyclone2, i mean if the DCI is enabled in spartan3 will there be no need for that resistors when cyclone2 is driving the LVDS line?
The LVDS_DCI should work as the end termination (rather than LVDS_DT), but I'm not 100% sure all LVDS drivers will be compatible with it. The issue is that the DCI attempts to force the common-mode level at the receiving end -- whereas normally this is only controlled by the driver.
The other questions you're asking indicate (to me) that this project may be too difficult for you to complete successfully. I suggest you learn more about the things I discussed in the previous post. Your chances, now, of getting a 622Mbps bus working are slim to none.
If you are running your bus as DDR, take a look at Xilinx XAPP265. Otherwise check out XAPP622 for SDR. Regardless, XAPP265 has some good tips toward the end on how to use the DCM to adjust your clock and center it in the data valid window.
I'd think twice about using the DCI on the S3 and expecting it to work well as an LVDS term . You are better off using discrete resistors. Even better would be to jump to the S3E, which has LVDS_DT inputs available. The
3-resistor network is just an attenuator network at the source to translate full 2.5v or 3.3V levels to the LVDS levels; I suppose you could put it at the end of the line if it produced the required LVDS_25 levels (which it is supposed to), but that is a lot of stuff to bunch up under the chip. You do realize that the stub length on the terminators (to the pin) is kind of important, no?
Hi Dave, The placement of the fpga for chip to chip lvds in my board is about 1 to 1.5inch (distance), is that not possible? Anyhow, i don't really need such bandwidth for now, just want to make sure everything works fine, BTW, does a 100mil trace mismatch would work for LVDS pair? Thats approx. 25ps delay right?