configuration for a mixed mode VHDL-verilog lang

Hi all

My problem is I'd like to choose a VHDL file instantiated inside verilog via VHDL configuration

To summerize: I have a hierarcy: "top:vhdl - verilog - Verlog -vhdl: bottom" How to write a vhdl configuration to select the file for the bottom instantiation?

Rakesh YC