hi, ive completed a introductory book on vhdl, but not mature enough to do a real world complex designs using vhdl. i've been serching for tutorial guids to learn advanced vhdl, preferebly with case studies, but found non. most of the books on vhdl are introductory level. Some advanced vhdl books such as "The Designer's Guide to VHDL" does not consider sysnthesis aspect much. beacause of this lack of resources, im planning to shift from VHDL to verilog. The book "Advanced Digital Design with the Verilog" seems to cover what im looking for and has a good rating with amazon.
i need to know whther there are books such as this one for vhdl language. and a little comparison between vhdl and verilog based on the popularity for developing advanced deigital systems and support given by various software tools ( such as xilinx tools, modelSIM, etc)
and any comments on the verilog book im talking about.
thank you