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Xilinx 804 Aurora vhdl Design patch

Hi,

I'm using Xilinx 804 aurora vhdl design and I saw that on their web-site that there was a patch for it (Record Number: 18554) but the file is not available on their server anymore. I asked them and they seem to have problem finding it back. If any of you sees what I mean and has downloaded the patch called aurora_804_sp_patch.zip Could you let me know and I'll contact you directly (I'm not too fond of spam).

Best regards,

Jeremie.

Reply to
Jeremie Veyret
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Hi Jeremie,

I'm sorry to say that the zip file you are looking for only contains a Verilog version of the patch. It was originally produced by special request for a customer who could not upgrade to one of our newer designs: they had made custom changes to the old module.

In general we recommend an upgrade to one of the modules from the Xilinx Core Generator tool - these are the smallest Aurora designs we offer, and have the same interface as the old designs. I would be happy to create a VHDL version of the patch for you. If you contact me directly or pass the message along via your FAE or hotline, I'll do my best to help you out.

In hindsight, we should have provided both languages in the zip file. We're working to fix the broken link on the server - when its up and running again, we'll add the VHDL version of the patch to the zip file.

Cheers, Nigel

Jeremie Veyret wrote:

Reply to
Nigel Gulstone

Hi Nigel,

Thanks for the quick answer. I have a webcase opened to try to get the latest vhdl design out of Coregen and if I can get them no need for me to fix this old design. So far with Coregen I could only generate and test the code for single lane design. In the meantime I thought I should fix the old 4 lane design to prove the

4-lanes solution. So far it works with almost random data and I guess this patch is all I'm missing. I don't want to waste your time doing the conversion. A verilog patch will be fine. If it is an easy fix I'll convert it to the vhdl if not I'll wait for the webcase to help me to get the latest design. If you have the file I'll be glad if you can forward it to me. I'll send you an e-mail so that you get my address.

Thanks and Best Regards,

Jeremie.

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Reply to
Jeremie

Hi Jeremie,

For the benefit of anyone else who might be following this thread, the files I sent you are now also available on the Xilinx support page. The to the record with the patch is

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It was also good to hear that you were able to generate 4-lane modules from Coregen after your webcase was resolved :)

Best Regards,

Nigel

Jeremie wrote:

Reply to
Nigel Gulstone

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