I'm having trouble trying to figure out why this VHDL synthesizes to something which generates glitches when post-route simulated in Modelsim.
Regardless of what I do, I always get tons of warnings from VitalGlitch in Modelsim about glitches on slices involving "count". I am using Precision to synthesize. These tools are all part of Lattice ispLever v7.0. The clock is 1MHz. This is supposed to be a simple divide by 100 counter.
I don't actually see any glitches as written (although they are reported by modelsim). However, if I remove the range restriction on count, I do see some glitches (this is all in sim...I have not checked for glitches in the actual HW).
Here's the code:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
entity Tester is PORT (
CLK: IN std_logic; RESET: IN std_logic; CS: IN std_logic; OUTP: OUT std_logic; QA0_d: OUT std_logic; QA1_d: OUT std_logic); end;
architecture RTL of Tester is
COMPONENT clock IS --Divides 1MHz clock down to 10KHz PORT (
--Inputs CLK1M: IN std_logic; --1MHz clock RESET: IN std_logic; --Active Low
--Outputs CLK10K: OUT std_logic); --10KHz clock END COMPONENT; begin div: clock PORT MAP ( CLK1M => CLK, RESET => RESET, CLK10K => OUTP); QA0_d