Error in MAP (Xlinx Project navigator)

Hi All, when I synthesize my design in xilinx project navigator, I get an error message, "ERROR:MapLib:681 - LOC constraint Y4 on SW is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

However when I open the Xilinx Pace editor, I can see that the pin exists. Does anyone know how to rectify this error.

Thanks, Shantha