Intermittent failures seen when bringing a clock into V4LX160 through IBUF to DCM

I'm currently working on a design where there isn't an available GC pin to bring a clock in (bad design, not mine). It's an 80MHz single- ended clock, but the design requires an 80MHz and 120MHz clock, so I need a DCM. This design has been proven working on another platform that allows me to bring the clock into a GC pin. When I try the design on the platform that does not allow the GC pin, I go through an IBUF to a DCM and then to BUFG's. There are intermittent failures seen when testing this design. After reading through the latest V4 user guide, it seems that going from an IBUF to a DCM is perfectly valid, but the DCM will be unable to successfully deskew the output clocks wrt the input. This design has an internal loopback mode in which case the skew on these clocks should not matter because they are no longer being used to clock in/out IOB data. Even in this mode, intermittent failures are seen, which leads me to believe it's not a skew issue, but rather just an intermittently dirty clock.

I tried going into a CC pin to a BUFIO, then BUFR, then into the DCM, but the design failed to route so I don't think BUFR's are able to drive DCM input clocks. The clock is forwarded over from another FPGA, and I've already tried different drive strength and slew rate combinations on the driving device just because I'm running out of ideas. Nothing seemed to make any differences.

Please let me know If anyone has any suggestions.

Reply to
Loading thread data ...

What's bad about that?

What sort of failures do you intermittently have? Describe what happens. Cheers, Syms. p.s. Are you the bwilson out of the Beach Boys? You were very good last year at the Bridge School Benefit! I expect you'll be adding "Surfin' FPGA" to your repertoire.

Reply to

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.