Xilinx clock IOB Place Error 645

-- Creates an ERROR:Place:645 if UCF file LOCs pins to non clock inputs

-- cam1_xclk_ibufd_inst : IBUFDS

-- port map (

-- O => cam1_xclk, -- to DCM input

-- I => gpio_exp_hdr2(7),

-- IB => gpio_exp_hdr2(6) );

-- This code didn't help the ERROR:Place:645 / WARNING:Place:644 problem

-- Does improve the route if one moves the pins to a clock input

-- cam1_xclk_ibufgds_inst : IBUFGDS

-- generic map (

-- -- DIFF_TERM => "FALSE", -- Differential Termination (Virtex-4 only)

-- -- Above line created a TYPE error

-- -- Language Template differs from v4ldl libraries guide.

-- -- IBUF_DELAY_VALUE => "0",

-- -- Specify the amount of added input delay for buffer,

-- -- "0"-"16" (Spartan-3E only)

-- IOSTANDARD => "DEFAULT")

-- port map (

-- O => cam1_xclk,

-- I => gpio_exp_hdr2(7),

-- IB => gpio_exp_hdr2(6));

-- This code does not get rid of WARNING:Place:644 but

-- does improve the appearance of the internal clock route

-- even though the UCF file has the pins LOC to non clock inputs

cam1_xclk_ibufd_inst : IBUFDS port map ( O => cam1_xclk_intermediate, I => gpio_exp_hdr2(7), IB => gpio_exp_hdr2(6) );

cam1_xclk_bufg : BUFG port map ( O => cam1_xclk, -- to DCM input I => cam1_xclk_intermediate );

Brad Smallridge aivision.com

And then there is this:

cam1_dcmfx2 : dcmfx2 port map( clkin_n_in => gpio_exp_hdr2(6), -- cam1_xclk, clkin_p_in => gpio_exp_hdr2(7), -- cam1_xclk, rst_in => reset, clkfx_out => cam1_clk7x, clkin_ibufgds_out => open, clk0_out => cam1_xclk, locked_out => cam1_lock7x );

generated clock with external differential inputs selected