Xilinx clock IOB Place Error 645

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I am getting this error.

ERROR:Place:645 - A clock IOB  clock component is not placed at an optimal
   IOB site  The clock IOB component <gpio_exp_hdr2<7>> is placed at site
   IOB_X0Y57. The clock IO site can use the fast path between the IO and the
   Clock buffer/GCLK if the IOB is placed in the master Clock IOB Site. If
   sub optimal condition is acceptable for this design you may set the
   environment variable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING to demote this
   message to a WARNING and allow your design to continue.

I did the Control Panel, System, Advanced, Environment Variables, System
varaible, New,
Varaible Value SET  ? This worked but is SET necessary or just having the
variable name there enough?

This reduced the error to a warning.

Is there a way to get around this without this cryptic ritual?

Are there any clock inputs brought to headers on the ML403 or will I have to
expand my board over to the DIFF CLK IN area and somehow tie into the SMA
connectors there? Is there a way I can add a clock buf to the input I
already have on the header?  The signal is actually fairly slow since it
frames the data, not clocks it.  I feed it to a DCM to generate a clock
signal internally.

Brad Smallridge

Re: Xilinx clock IOB Place Error 645
-- Creates an ERROR:Place:645 if UCF file LOCs pins to non clock inputs
-- cam1_xclk_ibufd_inst : IBUFDS
-- port map (
--   O  => cam1_xclk,  -- to DCM input
--   I  => gpio_exp_hdr2(7),
--   IB => gpio_exp_hdr2(6) );

-- This code didn't help the ERROR:Place:645 / WARNING:Place:644 problem
-- Does improve the route if one moves the pins to a clock input

-- cam1_xclk_ibufgds_inst : IBUFGDS
-- generic map (
-- --   DIFF_TERM => "FALSE",    -- Differential Termination (Virtex-4 only)
-- --    Above line created a TYPE error
-- --    Language Template differs from v4ldl libraries guide.
-- --   IBUF_DELAY_VALUE => "0",
-- --  Specify the amount of added input delay for buffer,
-- --   "0"-"16" (Spartan-3E only)
-- port map (
--   O  => cam1_xclk,
--   I  => gpio_exp_hdr2(7),
--   IB => gpio_exp_hdr2(6));

-- This code does not get rid of WARNING:Place:644 but
-- does improve the appearance of the internal clock route
-- even though the UCF file has the pins LOC to non clock inputs

   cam1_xclk_ibufd_inst : IBUFDS
 port map (
   O  => cam1_xclk_intermediate,
   I  => gpio_exp_hdr2(7),
   IB => gpio_exp_hdr2(6) );

 cam1_xclk_bufg : BUFG
 port map (
   O => cam1_xclk,  -- to DCM input
   I => cam1_xclk_intermediate );

Brad Smallridge

Re: Xilinx clock IOB Place Error 645
And then there is this:

 cam1_dcmfx2 : dcmfx2
 port map(
  clkin_n_in   => gpio_exp_hdr2(6), -- cam1_xclk,
  clkin_p_in   => gpio_exp_hdr2(7), -- cam1_xclk,
  rst_in       => reset,
  clkfx_out    => cam1_clk7x,
  clkin_ibufgds_out  => open,
  clk0_out     => cam1_xclk,
  locked_out   => cam1_lock7x );

generated clock with external differential inputs selected

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