I'm using XST 8.1 SP3 with a Spartan3 design. I'm trying to use both the output and tri-state flip-flops in the IOB, but the Xilinx tools are fighting me.
If I code my logic as:
always @(posedge ifclk) amb_data_enable
Xilinx Map vs IOB tri-state with clock enable...
Apr 25, 2006
1 Replies
Here's more info....
I re-coded to get rid of the clock enable thinking that would trivially fix my problem:
reg data_on; wire data_enable; always @(posedge ifclk) if (dclkp) data_on
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