Xilinx Map vs IOB tri-state with clock enable...

I'm using XST 8.1 SP3 with a Spartan3 design. I'm trying to use both the output and tri-state flip-flops in the IOB, but the Xilinx tools are fighting me.

If I code my logic as:

always @(posedge ifclk) amb_data_enable

Reply to
johnp
Loading thread data ...

Here's more info....

I re-coded to get rid of the clock enable thinking that would trivially fix my problem:

reg data_on; wire data_enable; always @(posedge ifclk) if (dclkp) data_on

Reply to
johnp

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.