I'm running into a problem trying to use the output registers in a Xilinx IOB and am hoping someone has seen/solved this before.
An original verion of my code worked just fine and XST pushed the registers into the IOB: //synthesis attribute IOB of sram0_a is "TRUE" always @(posedge clk_mem) begin sram0_a[19:1]
Howdy John,
I can't help you with what might be causing the behavior, but until you figure that part out, perhaps you can work around it by putting a reset or enable signal on flops for one of the address buses but not the other. Of course, the reset or enable has to be tied to something that the tool thinks could dynamically change (even _you_ know it doesn't change) so that it doesn't optimize out!
Have fun,
Marc
Perhaps u could declare two independent always blocks. I believe the optimization is occuring because it is defined in the same always block.
always @(posedge clk_mem) begin sram0_a[19:1] end
-- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USA
I found the answer after more dinking around.
You need to use the option: //synthesis attribute equivalent_register_removal of sram0_a is no; //synthesis attribute equivalent_register_removal of sram1_a is no;
John P
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