ISE Testbench/Schematic Generation ignores package

Using the Xilinx Project Navigator, I created a project and added a package definition (vhd-file) at the very top level. Inside this package I defined some types of integers, signed and unsigned. I included this package in all other vhd-files of the project with "use my_package.all". All syntax checks were successfull. Now the problem: When I automaticaly create a Schematic or a Testbench file, the package definitions seem to be ignored: all ports defined in the original vhd-file as integers (8bit) are now only std_logic. This can be seen directly in the schematics drwaing, or the testbench grafical display or the testbench vhd-file. I get an error message saying: "Compiling vhdl file ##_top.vhd in Library work. ERROR:HDLParsers:3014 - ##_top.vhd Line 9. Library unit my_package is not available in library work. WARNING:HDLParsers:3465 - Library as no units. Did not save reference file xst/work/hdllib.ref for it."

Does anyone know where the error is located?

-- __________________________________________ Dipl.-Ing. Hanns-Walter Schulz TU Braunschweig Institut fuer Luft- und Raumfahrtsysteme Institute of Aerospace Systems Hermann-Blenk-Str. 23 Tel.: ++49 531 391 9968 D-38108 Braunschweig Fax: ++49 531 391 9966

Seems I can't attach files in the newsgroup. The problem is as follows: I have defined the types uint8 and uint16 in "mavision_package.vhd". I use these to define the ports of "mavision_top.vhd". If I check syntax for "mavision_package.vhd" and "mavision_top.vhd", I get no warnings or error messages from ISE. But, if I try to automatically derive a Test Bench Waveform from "mavision_top.vhd", all uint8 and uint16 ports are defined as std_logic ports. This can be seen in "TBW1.tbw" or "TBW1.vhw". This is the reason, why I cant run a simulation.

Where's the mistake?

Here are the package an the main file:

################################################################################ package ################################################################################

library IEEE; use IEEE.STD_LOGIC_1164.all;

package mavision_package is

type uint8 is range 255 downto 0; type sint8 is range 127 downto -128;

type uint16 is range 65535 downto 0;

end mavision_package;

################################################################################ main ################################################################################ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM; use UNISIM.VComponents.all;

library mavision_lib; use mavision_lib.mavision_package.all;

entity mavision_top is port (CLK_Pixelclock : in std_logic; Data_in : in uint8; LVAL : inout std_logic; FVAL : inout std_logic; PVAL : out std_logic; ROWS : out uint16; COLS : out integer );

end mavision_top;

architecture Behavioral of mavision_top is

component tstr is port (CLK_Pixelclock_S : in std_logic; Data_in_S : in uint8; LVAL_S : inout std_logic; FVAL_S : inout std_logic; PVAL_S : out std_logic; ROWS_S : out uint16; COLS_S : out integer ); end component tstr;

begin tstr_1 : tstr port map (CLK_Pixelclock_S => CLK_Pixelclock, Data_in_S => Data_in, LVAL_S => LVAL, FVAL_S => FVAL, PVAL_S => PVAL, ROWS_S => ROWS, COLS_S => COLS );

end Behavioral;

################################################################################

I really would appreciate if you'd find the time to have a look at it.

Greets, Hanns-Walter

"Dipl.-Ing. Hanns-Walter Schulz" schrieb im Newsbeitrag news:d3o61m$7d2$ snipped-for-privacy@rzcomm2.rz.tu-bs.de...

"Dipl.-Ing. Hanns-Walter Schulz" schrieb im Newsbeitrag news:d3o61n$7d2$ snipped-for-privacy@rzcomm2.rz.tu-bs.de...