I am using using the Xilinx project navigator Version 6.2i for writing the VHDL code and synthesize it .I am facing a problem with the signals defined with the real data type.The navigator indicates that the code (with some signals defined as real ) is syntactically correct but it gives an error during synthesis.It states this feature is not supported. After checkin out for a solution we ended up finding that a math_real package in ieee.std_logic_1164.all is copyright protected.So actually am unable to understand wat to do to get teh package.
- posted
17 years ago