I have two questions regarding the code bellow.
I need a dual port buffer (4Kx32 write only, 8Kx16 r/w port). I have instanciated 8 block RAMS as the code bellow shows:
------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all;
entity acqbuf is Port ( i_Clk : in std_logic; i_AddrA : in std_logic_vector(11 downto 0); i_DataInA : in std_logic_vector(31 downto 0); i_WrEnA : in std_logic; i_EnA : in std_logic; i_WrEnB : in std_logic; i_EnB : in std_logic; i_AddrB : in std_logic_vector(12 downto 0); i_DataInB : in std_logic_vector(15 downto 0); o_DataOutB : out std_logic_vector(15 downto 0) ); end acqbuf;
architecture structural of acqbuf is component RAMB16_S2_S4 -- pragma translate_off generic ( WRITE_MODE_A : string := "WRITE_FIRST" ; WRITE_MODE_B : string := "WRITE_FIRST" ; ); -- pragma translate_on port ( DIA : in std_logic_vector (1 downto 0); ADDRA : in std_logic_vector (12 downto 0); ENA : in std_logic; WEA : in std_logic; SSRA : in std_logic; CLKA : in std_logic; DOA : out std_logic_vector (1 downto 0); -- DIB : in std_logic_vector (3 downto 0); ADDRB : in std_logic_vector (11 downto 0); ENB : in std_logic; WEB : in std_logic; SSRB : in std_logic; CLKB : in std_logic; DOB : out std_logic_vector (3 downto 0) ); end component; attribute BOX_TYPE of RAMB16_S2_S4 : COMPONENT is "BLACK_BOX";
begin
RAM : for i in 0 to 7 generate U_RAMB16_S2_S4 : RAMB16_S2_S4 port map ( DIA => i_DataInB(i*2+1 downto i*2), ADDRA => i_AddrB, ENA => i_EnB, WEA => i_WrEnB, SSRA => '0', CLKA => i_Clk, DOA => o_DataOutB(i*2+1 downto i*2), -- DIB => i_DataInA(i*4+3 downto i*4), ADDRB => i_AddrA, ENB => i_EnA, WEB => i_WrEnA, SSRB => '0', CLKB => i_Clk, DOB => open ); end generate; end structural;
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Whereas this code compiles with no error under ISE, under Modelsim I get the following result:
do acqbuf_tb.fdo # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity acqbuf # -- Compiling architecture structural of acqbuf # ** Error: acqbuf.vhd(33): near ")": expecting: IDENTIFIER # ** Error: D:/Modeltech_xe_starter/win32xoem/vcom failed. # Error in macro ./acqbuf_tb.fdo line 5 # D:/Modeltech_xe_starter/win32xoem/vcom failed. # while executing # "vcom -93 -explicit acqbuf.vhd # "
The only way to fix it I have found is commenting the generic section. Is there a decent way to do it keeping that section?
The second question is fairly (rather?) newbie: how to define the attributes for the instanciated blocks? I suppose the declarationos in the generic section aren't enough to guarantee the instanciated components behave like I mean them to.
I tried to do it as in the snippet bellow and I get compilation error:
RAM : for i in 0 to 7 generate attribute WRITE_MODE_A : string; WRITE_MODE_A of URAMB16_S2_S4 : lable is "WRITE_FIRST"; attribute WRITE_MODE_B : string; WRITE_MODE_B of URAMB16_S2_S4 : lable is "WRITE_FIRST";
U_RAMB16_S2_S4 : RAMB16_S2_S4 port map ( DIA => i_DataInB(i*2+1 downto i*2),
Thank you in advance for your help.
Elder.