Finally I got simulation of logicores in webpack 9.1.03i to work with the ISE simulator. However, these messages appear in the transcript window:
Running Fuse ... WARNING:HDLParsers:3583 - File "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" which file "C:/Xilinx91i/theller/mydesign/divider.vhd" depends on is modified, but has not been compiled. You may need to compile "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" first. Compiling vhdl file "C:/Xilinx91i/theller/mydesign/detector.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. WARNING:HDLParsers:3583 - File "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" which file "C:/Xilinx91i/theller/mydesign/divider.vhd" depends on is modified, but has not been compiled. You may need to compile "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" first. WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" which file "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" first. WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" which file "C:/Xilinx91i/theller/mydesign/detector.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" first. WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" which file "C:/Xilinx91i/theller/mydesign/detector.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" first. Compiling vhdl file "C:/Xilinx91i/theller/mydesign/detector_tbw.vhw" in Library work. Entity compiled. Entity (Architecture ) compiled. Parsing "detector_tbw_beh.prj": 1.84 Codegen work/detector: 0.00 Codegen work/detector/Behavioral: 0.41 Codegen work/detector_tbw: 0.00 Codegen work/detector_tbw/testbench_arch: 0.34 Building detector_tbw_isim_beh.exe Running ISim simulation engine ... This is a Lite version of ISE Simulator. Simulator is doing circuit initialization process. Finished circuit initialization process.
Apparently this file "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" isn't present on my system, it is probably a filename in Xilinx source code. How can I recompile this file???
Other files like these "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd"
*are* present on my system, but *I* did not change them.How can it be that they need to be compiled? How would I compile them? Do I have a broken installation? Or should I not be bothered at all by these messages?
Thanks for any help, Thomas