Soft CPU vs Hard CPU's

Hai all, I heard that the SOFT CPU's have wide range of benefits than the HARD CPU's. if so, then why still HARD CPU's are preferred.

plz let me know the answer.

regards, kishore

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Hi (hai means "shark" in my native language)

1 your question doesnt have an answer. 2 and your assumptions are not correct. 3 and if you keep using an identy like "teen" what hardly is your name and wording in style 'Hai', 'plz' then you hardly will get answers to anything you ask. If you dont understand what I mean then it would be of benefit for you to go back to school and learn there something. 4 if you do not get upset to what I said above and do some homework then you will be able to correct your wrong assumptions and answer your question yourself.


"teen" schrieb im Newsbeitrag news:

Reply to
Antti Lukats

You heard wrong. A hard CPU is faster and cheaper then a soft CPU. By cheaper I mean they take much less die area then an equivalent soft CPU. The downside of the hard CPUs is that they are only available in high end FPGAs like the Virtex2P and Virtex4. The cheaper FPGAs like the Spartan3 don't have embedded CPUs. If you needed a processor in a Spartan3 you would have to use a soft CPU, however you want to use one that was much simpler then the PPC in the Virtex2Ps and 4s. If you implemented a full PPC you would use so many slices that you would negate the cost advantage of the Spartan3.

Reply to
General Schvantzkoph


That is the main reason why Hard CPU's are still used. They are cheaper.... a Phillips Arm 7 32 bit CPU is about $3.50 in quantity. An FPGA with a similar size softcpu like a Microblaze is about $10.

Soft CPU's are used for performance. They take advantage of the FPGA's logic and use parallelizm to speed up operatiations (ie multipuly two

32 bit numbers in a single clk cycle). A hard CPU would take 4 or more clk cycles to multiply two 32bit numbers.

So SoftCPU's used with FPGA logic can have a higher performance than an equivelent hardCPU.

So it totally depends on your application to whether a soft or hard CPU is for you.


Reply to

SoftCPUs also can have custom peripherals (ie 5 x UARTs, 6 x SPI bues,

20 x I2C bues).

With a Hard CPU your stuck with what the manufacturer gives you.

Personally SoftCPU's are more fun.... custom home brewed CPU's are exciting!!!

Writing a VHDL model of a CPU is the closest to designing my own CPU I'll ever get. There is something exciting about that!!!!


Reply to

Er, that is designing a CPU! Probably the large majority of commerical CPUs are synthesizable, or contain a lot of synthesizable code.

Cheers, Jon

Reply to
Jon Beniston

Hey Antti,

Don't beat about the bush, man - tell him what you think, straight up! This softly-softly approach never works [grin]

[Not to say that I don't agree with your points on the language though :-]


Reply to

True enough, but it seems to me an external (or on-chip) hard CPU loosely coupled with a "coprocessor" built of FPGA fabric gives you the best of both worlds for performance/cost and also minimizes power and you don't need lots of address pins going into the FPGA.


Reply to
Jeff Cunningham

Spartan 3E should help with this. The smallest Spartan 3E starts at under $2 in quantity (and fits a small MicroBlaze system) for an effective MicroBlaze cost of $.48 [1]. You may need a larger device to get everything you want, but I did want to point out that the $10 is a little high if one is going primarily for cost. It is not fair to compare the entire cost of the FPGA to just a hard processor and then use the rest of the FPGA for other stuff. In this case the FPGA is doing a lot more than the hard processor.

As far as the benefits of a soft processor. MicroBlaze is highly configurable. You can turn on the features you need: instruction cache, data cache, FSL, XCL, FPU. See

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for more information on MicroBlaze v4.00.a.

The other huge advantage of soft processors is the FPGA architecture itself. EDK has an FSL wizard to allow easy creation of accelerators. With careful acceleration of one's application, one can obtain performance that no hard processor can touch.

EDK also includes a lot of other IP allowing one to build a System On a Chip (SoC) out of the box. It is a great deal for the price.

Personally, I also find debugging on an FPGA a lot easier. One can simulate the EDK system and get a ton of information. I find ChipScope a lot more convenient than a logic analyzer and one can dig a lot deeper. Tracking down a bus issue on a hard processor can be a pain. On both sides there are lots of good tools if you want to spend the money, but I think the costs may be more reasonable on the FPGA side.

If you have the need, Xilinx will sell the MicroBlaze source code for you to customize as you see fit. Try doing that at a reasonable price on a hard processor.

I am not in marketing or sales, but I have no problem listing some of the advantages of soft processors.

This post is my own opinion, and not an official Xilinx post. Reverse domain and remove the NOSPAM from e-mail address to respond by e-mail.

[1] Xil> Cost!!!!
Reply to
Benjamin J. Stassart

"*500K unit volume, second half 2006" !!!

plus you have to factor in the cost of:

- the configuration prom - extra regulators that you wouldn't need with most micros - analog peripherals - possibly an oscillator - possibly some external RAM

It's not quite a simple as multiple cost-per-LUT by the number of LUTs used.

Cheers, Jon

Reply to
Jon Beniston

... and neatly avoided ANY mention of the memories needed to actually RUN the '48c core'.

Soft CPUs are great for consuming LUTs, and FPGA vendors love them, but they are very much 'stone soup'.

Key deployment 'reality check' questions are :

** Is there a key operational plus, to having the CPU on the FPGA ? ** Can I use a smaller FPGA, if I jettison the Soft CPU ? [Suddenly that claimed 48c CPU can get very expensive ! ] ** Will I get less EMC, if I chose a uC with on-chip, secure FLASH code, vs a FPGA ? [ that also needs short lifetime, off chip SDRAM, that must be loaded from another NV memory -> you have to pay twice to store your less secure code !] ** Can I afford the IDLE power budget to run the soft CPU ?

eg take a hard look at the new widely sourced Flash ARMs (for example), that include Large Secure FLASH, AND Analog peripherals, AND Oscillators, AND save a LOT of power (wrt Spartan 3E et al). All for less than the cost of the dual-CODE memory the Soft-CPU needed....


Reply to
Jim Granville

Hello Antti,

Thank you for your reply. I had disclosed my identity in the mail(regards, Kishore) . Please read the mail again.

Also I competely disagree with your assumption that I haven't done any homework. After I had gone through a couple of pages collected through I had some ambiguity in the differences between the two CPU's , So I had asked the above question only to refine my web searching.

Pease be straight forward while giving any suggestions.

Regards, Kishore

Reply to


Quite frankly, you have not even scratched the surface of the issue you are asking about. There is probably ten years of research, results, products, etc. that you need to demonstrate a minimum of understanding of.

There is another twenty years of hardware uP knowledge that you seem to be totally unaware of.

The question itself speaks volumes.

Open your mouth, and you remove all doubt of your competence.

So, now that we know you know practically nothing, we can reply with something that will help you.

FPGAs have long been known to take thirty transistors to do the job of a single transistor in an ASIC. The same is true for a microprocessor. It takes many more tranistors to the the job in an FPGA, than it does in a uP.

Why would anyone in their right mind then use a FPGA?

Because it can be anything, for anyone (it is programmable).

An ASIC requires a great up front investment, and if anything is wrong, you pretty much throw most of it away, and start over. An ASIC also requires a task that is not going to change -- ever. Fine for a uP that has a language that no one will change (too many lines of code already written for it), but a system is always changing.

NTT saved billions of dollars by using Xilinx FPGAs in their cellular base stations: they didn't have to remove all the equipoment from the field every time there was a change, they merely reprogrammed all the base stations.

No genius required to see this advantage.

So why use a soft uP at all?

A uP is standard, so you don't need to change it, it uses software to program it (hence the flexibility is maintained), and it is going to be much faster, much smaller, and much lower power if the uP is hardened (made into a non-changing mask).

Answer is, that unless you want to make a uP with a custom instruction set (that now limits us to probably less that .001% of all applications

- and for them we offer the APU interface), there is no good reason.

Hence why we offer the IBM 405 PPC in Virtex II Pro, and Virtex 4.

But, what if I can replace a ton of gates and flip flops by a simple program (less than 1K words of instruction)? Hey, maybe there is a benefit to using a soft uP: I can actually use less area/power/gates/transistors in the FPGA with a soft uP, than I would use if I used FPGA logic to do the same job.

Hence the fabulous sucess of the simple microcontroller core IP that we offer for both the 405 PPC, and MicroBlaze.


teen wrote:

Reply to

Another reason, of course, to use a soft processor.. is one like mine... I needed a processor.. nothing complex... But I have an FPGA only 1.2 full.. So I've got a picoblaze .. with a dual port RAM to handle inter processor communication, a simple interpreter to handle initialization, and an interrupt controller to handle unscheduled, but necessary events.. and a real cool SPI interface which automatically reconfigures itself depending on what external device is chip selected.

And it was free.. because the FPGA has to be there, so I saved myself a few bucks and impressed my boss :-).


Reply to
Simon Peacock

That is not entirely true. Similar to FPGAs uP are extremly inefficient because they are universal.

If I want to add two numbers in a uP, something that basically takes a few dozen gates, thousands of of gates start working. Lot's of stuff that is there to preform the ISA abstraction like instruction reordering, scoreboards and reservation stations. Security measures like MMU, and stuff to hide memory access time like caches and translation lookaside buffers. At the same time many, many more gates are sitting around idle like unused cache parts and unused execution units. In a high and processor it takes half a billion transistors to execute something like six operations per clock cycle. But it is universal an can run any algorithm any time.

On the other extreme you have an asic implementation of the algorithm that only does work that is required for the task but can do nothing else. This of course is a lot more efficient. (By a factor of 100.000 or so for many algorithms)

The FPGA is a compromise between the two. It can use asic like algorithms getting away without all the CPU overhead stuff but you have to pay the factor of thirty for the implementation because you can change the algorithm universaly.

As a result it takes a lot - and I mean a lot - less transistors per operation e.g. to perform a smith-waterman computation in an FPGA than in a uP.

Kolja Sulimma

Reply to
Kolja Sulimma


I respectfully disagree.

If I want a uP, I can optimize it until I have only those transistors I need.

If the job is to run any program whatsoever, I can not choose to implement just the logic I need, as that would be an infinite amount fo logic (for an unbounded set of programs).

Now that I have an instruction set defined, it takes far more transistors to do the same in a FPGA, than in a ASIC uP (or ASSP uP).

Aust> Not really related to the original question but intresting nonetheless:

Reply to
Austin Lesea

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